|
Details, datasheet, quote on part number:FTT1010-M
| |
Datasheet text preview:
IMAGE SENSORS
FTT1010-M Frame Transfer CCD Image Sensor
Product specification File under Image Sensors 1999 September 21
Philips Semiconductors
TRAD
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
· · · · · · · · · · · · · ·
1-inch optical format 1M active pixels (1024H x 1024V) Progressive scan Excellent anti-blooming Variable electronic shuttering Square pixel structure H and V binning 100% optical fill factor High dynamic range (>72dB) Description High sensitivity Low dark current and fixed pattern noise Low read-out noise Data rate up to 2 x 40 MHz Mirrored and split read-out
The FTT 1010-M is a monochrome progressive-scan frame-transfer image sensor offering 1K x 1K pixels at 30 frames per second through a single output buffer. The combination of high speed and a high linear dynamic range (>12 true bits at room temperature without cooling) makes this device the perfect solution for high-end real time medical X-ray, scientific and industrial applications. A second output c a n either be used for mirrored images, or can be read out simultaneously with the other output to double the frame rate. The device structure is shown in figure 1.
Device structure
Optical size: Chip size: Pixel size: Active pixels: Total no. of pixels: Optical black pixels: Timing pixels: Dummy register cells: Optical black lines: 12.288 mm (H) x 12.288 mm (V) 14.572 mm (H) x 26.508 mm (V) 12 µm x 12 µm 1024 (H) x 1024 (V) 1072 (H) x 1030 (V) Left: 20 Right: 20 Left: 4 Right: 4 Left: 7 Right: 7 Bottom: 6 Top: 6
Z
6 black lines Image Section
Y
1024 active lines 4 20 2060 lines
20 4 1024 active pixels
Storage Section
W
Output 7 amplifier
6 black lines 1072 cells Output register
X
7
Figure 1 - Device structure
1999 September
2
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Architecture of the FTT1010-M
The FTT1010-M consists of a shielded storage section and an open image section. Both sections are electronically the same and have the same cell structure with the same properties. The only difference between the two sections is the optical light shield. The optical centres of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Output registers are located below the storage section. The output amplifiers Y and Z are not used in Frame Transfer mode and should be connected as not-used amplifiers. After the integration time the charge collected in the image section is shifted to the storage section. The charge is read out line by line through the lower output register. The left and the right half of each output register can be controlled independently. This enables either single or multiple read-out. Dur ing vertical transport the C3 gates separate the pixels in the register. The letters W, X, Y and Z are used to define the four quadrants of the sensor. The central C3 gates of both registers are par t of the W and Z quadrants of the sensor. Both upper and lower registers can be used for vertical binning. Both registers also have a summing gate at each end that can be used for horizontal binning. Figure 2 shows the detailed internal str ucture.
IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Geometric fill factor Image clock pins Capacity of each clock phase Number of active lines Number of black reference lines Number of dummy black lines Total number of lines Number of active pixels per line Number of overscan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line 17.38 mm 1:1 2 12.288 x 12.288 mm 12x12 µm2 100% A1, A2, A3, A4 2.5nF per pin 1024 2 4 1030 1024 8 (2x4) 40 (2x20) 1072
STORAGE SECTION Storage width x height Cell width x height Storage clock phases Capacity of each clock phase Number of cells per line Number of lines 12.864 x 12.360 mm2 12x12 µm2 B1, B2, B3, B4 2.5nF per pin 1072 1030
OUTPUT REGISTERS Output buffers (three-stage source follower) Number of registers Number of dummy cells per register Number of register cells per register Output register horizontal transport clock pins Capacity of each C-clock phase Overlap capacity between neighbouring C-clocks Output register Summing Gates Capacity of each SG Reset Gate clock phases Capacity of each RG 4 (one on each corner) 2 (one above, one below) 14 (2x7) 1072 C1, C2, C3 60pF per pin 20pF 4 pins (SG) 15pF 4 pins (RG) 15pF
1999 September
3
|
|
