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Details, datasheet, quote on part number:N74F225D
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INTEGRATED CIRCUITS
74F225 16X5 asynchronous FIFO (3-State)
Product specification IC15 Data Handbook 1992 Jun 15
Philips Semiconductors
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
FEATURES
· Independent synchronous inputs and outputs · Organized as 16 words of 5 bits · DC to 25MHz data rate · 3State outputs · Cascadable in wordwidth and depth direction
DESCRIPTION
This 80bit active element FirstInFirstOut (FIFO) is a monolithic Schottkyclamped transistortransistor logic (STTL) array organized as 16words of 5bits each. A memory system using the 'F225 can be easily expanded in multiples of 16words of 5bits as shown in Figure 1. The 3State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The 'F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the 'F225 is provided by three outputs, Input
Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are noninverting with respect to the data inputs and are disabled when the OE input is High. When OE is Low, the data outputs are enabled to function as totempole outputs. TYPICAL SUPPLY CURRENT ( TOTAL) 65mA
TYPE 74F225
TYPICAL fMAX 25MHz
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F225N N74F225D PKG DWG #
20pin plastic DIP 20pin plastic SOL
SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS CPA, CPB D0 D4 OE UNCPIN MR IR UNCPOUT Q0 Q4 DESCRIPTION Load clock A and load clock B inputs Data inputs Output enable input (activeLow) Unload clock input Master reset input (activeLow) Input ready output Unload clock output (activeLow) Data outputs 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 50/33 50/33 150/40 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 1.0mA/20mA 1.0mA/20mA 3.0mA/24mA 1.0mA/20mA
OR Output ready output NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
RESET MODE
A HightoLow transition on the Master Reset (MR) input invalidates all data stored in the FIFO by clearing the control logic and setting OR Low. This HightoLow transition on the MR input does not effect the data outputs but since OR is driven Low, it signifies invalid data on the outputs.
READ MODE
The Output Ready (OR) output is High when valid data is present on the data outputs. Data in the array is shifted on the LowtoHigh transition of the Unload Clock Input (UNCPIN). In order for Output Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be High.
WRITE MODE
Data may be written into the array on the LowtoHigh transition of either load clock (CPA or CPB) input. When writing data into the FIFO, one of the load clock inputs must be held High while the other strobes data into the FIFO. This arrangement allows either load clock to function as an inhibit for the other. Input Ready (IR) monitors the status of the last word location and signifies when the FIFO is full. This output is High whenever the FIFO is available to accept new data. The unload clock output (UNCPOUT) also monitors the last word location. This output generates a Lowlogiclevel pulse (synchronized to the internal clock pulse) when the last word location is vacant
June 15, 1992
2
853-1652 06992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
PIN CONFIGURATION
CPA IR 1 2 20 19 18 17 16 15 14 13 12 11 V CC CPB MR OR UNCPIN
IEC/IEEE SYMBOL
9 18 EN5 CT=0 CT0 & & 1 + G1 G2/Z3 2CT<16 4 5 FIFO 16 X 5 CTR 3 3
UNCPOUT 3 D0 D1 D2 D3 D4 OE 4 5 6 7 8 9
2 17 15 14 13 12 11
Z4
Q0 Q1 Q2 Q3 Q4
16 4 1D 5 6 7 8
GND 10
SF00334
SF00336
LOGIC SYMBOL
4 5 67 8
D0 D1 D2 D3 D4 1 19 16 9 18 CPA CPB UNCPIN OE MR Q0 Q1 Q2 Q3 Q4 IR OR UNCPOUT 3
VCC = Pin 20 GND = Pin 10
15 14 13 12 11 2 17
SF00335
June 15, 1992
3
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