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Details, datasheet, quote on part number:N74F2373N
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Datasheet text preview:
INTEGRATED CIRCUITS
74F2373 Octal transparent latch with 30 equivalent output termination (3-State)
Product specification Supersedes data of 1995 Jun 20 IC15 Data Handbook 1999 Feb 01
Philips Semiconductors
Philips Semiconductors
Product specification
Octal transparent latch with 30 equivalent output termination (3-State)
74F2373
FEATURES
· 8-bit transparent latch · 30 Ohm output termination for driving DRAM · 3-State outputs glitch free during power-up and power-down · Common 3-State output register · Independent register and 3-State buffer operation
DESCRIPTION
The 74F2373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 30 Ohm series termination on the outputs reduces over/undershoot, making them ideal for driving DRAM
The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output. When OE is high, the outputs are in high impedance "off " state, which means they will neither drive nor load the bus. TYPICAL PROPAGATION DELAY 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 35mA
TYPE 74F2373
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP 20-pin plastic SOL N74F2373N N74F2373D SOT146-1 SOT163-1 DRAWING NUMBER
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 - D7 E OE Q0 - Q7 Data inputs Enable input (active high) Output enable inputs (active low) 3-State outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 3.0mA/3.0mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 E
LOGIC SYMBOL
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 11 1 E OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 VCC = Pin 20 GND = Pin 10
5
6
9 12
15
16
19
SF00250
SF00251
1999 Feb 01
2
853-2140 20747
Philips Semiconductors
Product specification
Octal transparent latch with 30 equivalent output termination (3-State)
74F2373
IEC/IEEE SYMBOL
1 11 EN1 EN2 2 5 6 9 12 15 16 19
3 4 7 8 13 14 17 18
2D
1
SF00252
LOGIC DIAGRAM
D0 3 D E E 11 D1 4 D E D2 7 D E D3 8 D E D4 13 D E D5 14 D E D6 17 D E D7 18 D E
Q
Q
Q
Q
Q
Q
Q
Q
OE
1 2 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
VCC = Pin 20 GND = Pin 10
Q0
SF00256
FUNCTION TABLE
INPUTS OE L L L L L H E H H L L Dn L H l h X X INTERNAL REGISTER L H L H NC NC OUTPUTS Q0 - Q7 L H L H NC Z Hold Disable outputs outputs Latch and read register and read register OPERATING MODE MODE
Enable and read register and read register
H H Dn Dn Z NOTES: H= High-voltage level h= High state must be present one setup time before the high-to-low enable transition L= Low-voltage level l= Low state must be present one setup time before the high-to-low enable transition NC = No change X= Don't care Z= High impedance "off " state = High-to-low enable transition
1999 Feb 01
3
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