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Details, datasheet, quote on part number:N74F240D
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Datasheet text preview:
INTEGRATED CIRCUITS
74F240 Octal inverter buffer (3-State) 74F241/74F241A Octal buffer (3-State)
Product data Supersedes data of 1991 Jan 02 2002 Mar 18
Philips Semiconductors
Philips Semiconductors
Product data
Buffers
74F240/74F241/74F241A
FEATURES
· Octal bus interface · 3-State buffer outputs sink 64 mA · 15 mA source current · Guaranteed output skew less than 2.0 ns (74F241A) · Reduced ground bounce (74F241A) · Reduced ICC (74F241A only) · Reduced loading (74F241A IIL = 40 µA)
TYPE 74F240 74F241 74F241A TYPICAL PROPAGATION DELAY 4.3 ns 5.0 ns 4.5 ns
DESCRIPTION
The 74F240 and 74F241 are octal buffers that are ideal for driving bus lines of buffer memory address registers. The outputs are all capable of sinking 64 mA and sourcing up to 15 mA. The device features two output enables, each controlling four of the 3-state outputs. The 74F241A is functionally equivalent to its non-A counterpart. It has been designed to reduce effects of ground noise. Other advantages are noted in the features.
TYPICAL SUPPLY CURRENT (TOTAL) 37 mA 53 mA 32 mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL 20-pin plastic SSOP II COMMERCIAL RANGE VCC = 5 V ±10%, Tamb = 0 °C to +70 °C N74F240N, N74F241N, N74F241AN N74F240D, N74F241D, N74F241AD N74F240DB PKG DWG # SOT146-1 SOT163-1 SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS Data inputs (74F240) Ian, Ibn Data inputs (74F241) Data inputs (74F241A) OEa, OEb OEa, OEb Output enable inputs (Active-LOW) (74F240) Output enable input (74F241) Output enable input (74F241A) Yan, Ybn Yan, Ybn Data outputs (74F241, 74F241A) Data outputs (74F240) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.67 1.0/2.67 1.0/0.067 1.0/0.33 1.0/1.67 1.0/0.067 750/106.7 750/106.7 LOAD VALUE HIGH/LOW 20 µA/1.0 mA 20 µA/1.6 mA 20 µA/40 µA 20 µA/0.2 mA 20 µA/1.0 mA 20 µA/40 µA 15 mA/64 mA 15 mA/64 mA
Note to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
2002 Mar 18
2
8530355 27871
Philips Semiconductors
Product data
Buffers
74F240/74F241/74F241A
PIN CONFIGURATION FOR 74F240
OEa Ia0 Yb0 Ia1 Yb1 Ia2 Yb2 Ia3 Yb3 1 2 3 4 5 6 7 8 9 20 VCC 19 OEb 18 Ya0 17 Ib0 16 Ya1 15 Ib1 14 Ya2 13 Ib2
IEC/IEEE SYMBOL FOR 74F240
1 19 EN1 EN2 18 16 14 12 2 3 5 7 9
2 4 6 8 17 15
2D
1
12 Ya3 13 11 Ib3 11
GND 10
SF00320
SF00322
LOGIC SYMBOL FOR 74F240
2 4 6 8 17 15 13 11
LOGIC DIAGRAM FOR 74F240
Ia0 2 18 Ya0 Ib0 17 3 Yb0
Ia0 1 19 OEa
Ia1
Ia2
Ia3
Ib0
Ib1
Ib2 Ib3
Ia1
4
16
Ya1
Ib1
15
5
Yb1
Ia2 OEb Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3 Ia3
6
14
Ya2
Ib2
13
7
Yb2
8
12
Ya3
Ib3
11
9
Yb3
18 VCC = Pin 20 GND = Pin 10
16
14
12
3
5
7
9
OEa
1
OEb
10
SF00321
VCC = Pin 20 GND = Pin 10
SF00323
FUNCTION TABLE FOR 74F240
INPUTS OEa L L H Ia L H X OEb L L H Ib L H X OUTPUTS Ya H L Z Yb H L Z
NOTES: H = High voltage level L = Low voltage level X = Don't care Z = High impedance "off" state
2002 Mar 18
3
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