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Details, datasheet, quote on part number:N74F256D
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Datasheet text preview:
INTEGRATED CIRCUITS
74F256 Dual addressable latch
Product specification IC15 Data Handbook 1988 Nov 29
Philips Semiconductors
Philips Semiconductors
Product specification
Dual addressable latch
74F256
FEATURES
· Combines dual demultiplexer and 8-bit latch · Serial-to-parallel capability · Output from each storage bit available · Random (addressable) data entry · Easily expandable · Common reset input · Useful as dual 1-of-4 active High decoder
DESCRIPTION
The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data inputs, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs.
PIN CONFIGURATION
A0 1 A1 2 Da 3 Q0a 4 Q1a 5 Q2a 6 Q3a 7 GND 8 16 V CC 15 MR 14 E 13 Db 12 Q3b 11 Q2b 10 Q1b 9 Q0b
SF00805
TYPE
TYPICAL PROPAGATION DELAY 7.0ns
TYPICAL SUPPLY CURRENT (TOTAL) 28mA
74F256
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F256N N74F256D PKG DWG #
16-pin plastic DIP 16-pin plastic SO
SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS Da, Db A0, A1 E MR Q0a Q3a Port A, port B inputs Address inputs Enable (active Low) Master Reset inputs (active Low) Port A outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA 1.0mA/20mA
Q0b Q3b Port B outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1988 Nov 29
2
8530359 95207
Philips Semiconductors
Product specification
Dual addressable latch
74F256
LOGIC SYMBOL
IEC/IEEE SYMBOL
3 13 3 13 15 Z5 Z6 G4
Da 14 1 2 15 E A0 A1 MR Q0a Q1a Q2a Q3a
Db 1 0 0 G Q0b Q1b Q2b Q3b 2 1 0 3 1 2 3 14
5, 7D 1 C7 4R 4
5 6 7 6, 8D 1
4
5
6
7
9
10
11
12 0 1 2 3
C8 4R
9
10 11 12
VCC = Pin 16 GND = Pin 8
SF00806
SF00807
FUNCTION TABLE
INPUTS MR L L L L L H H H H H L X d q E H L L L L H L L L D X d d d d X d d d A0 X L H L H X L H L A1 X L L H H X L L H Q0 L Q=d L L L q0 Q=d q0 q0 OUTPUTS Q1 L L Q=d L L q1 q1 Q=d q1 Q2 L L L Q=d L q2 q2 q2 Q=d Q3 L L L L Q=d q3 q3 q3 q3 Addressable Latch Latch Store (do nothing) OPERATING MODE MODE Master Reset Demultiplex (active-High decoder when D=H)
H L d H H q0 q1 q2 Q=d = High voltage level = Low voltage level = Don't care = High or Low data one setup time prior to the Low-to-High Enable transition = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
1988 Nov 29
3
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