|
Details, datasheet, quote on part number:N74F259N
| |
Datasheet text preview:
INTEGRATED CIRCUITS
74F259 Latch
Product specification IC15 Data Handbook 1989 Apr 11
Philips Semiconductors
Philips Semiconductors
Product specification
Latch
74F259
FEATURES
· Combines demultiplexer and 8-bit latch · Serial-to-parallel capability · Output from each storage bit available · Random (addressable) data entry · Easily expandable · Common reset input · Useful as 1-of-8 active-High decoder
DESCRIPTION
The 74F259 addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the store mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data input, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs.
PIN CONFIGURATION
A0 1 A1 2 A2 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 8 16 V CC 15 MR 14 E 13 D 12 Q7 11 Q6 10 Q5 9 Q4
SF00823
TYPE
TYPICAL PROPAGATION DELAY 7.5ns
TYPICAL SUPPLY CURRENT (TOTAL) 31mA
74F259
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F259N N74F259D PKG DWG #
16-pin plastic DIP 16-pin plastic SO
SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D A0, A1, A2 E MR Data input Address inputs Enable input (active Low) Master Reset inputs (active Low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA
Q0 Q7 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1989 Apr 11
2
8530362 06316
Philips Semiconductors
Product specification
Latch
74F259
LOGIC SYMBOL
IEC/IEEE SYMBOL
1 2 3 14 13 1 2 3 13 15 D A0 A1 A3 9, 10D 10m 0R 9, 10D 10m 1R 9, 10D 10m 2R 9, 10D 10m 3R 9, 10D 10m 4R 9, 10D 10m 5R 9, 10D 10m 6R 4 5 6 7 9 10 11 12 2 G8 Z9 Z10 0 8M 0 7
14
E
15
MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
4
5
6
7
9
10
11
12
VCC = Pin 16 GND = Pin 8
9, 10D 10m 7R
SF00824
SF00825
FUNCTION TABLE
INPUTS MR L L L L · · · L H H H H · · · H L X d q H = = = = = E H L L L · · · L H L L L · · · D X d d d · · · d X d d d · · · A0 X L H L · · · H X L H L · · · A1 X L L H · · · H X L L H · · · A2 L L L L · · · H X L L L · · · Q0 L Q=d L L · · · L q0 Q=d q0 q0 · · · Q1 L L Q=d L · · · L q1 q1 Q=d q1 · · · Q2 L L L Q=d · · · L q2 q2 q2 Q=d · · · OUTPUTS Q3 L L L L · · · L q3 q3 q3 q3 · · · Q4 L L L L · · · L q4 q4 q4 q4 · · · Q5 L L L L · · · L q5 q5 q5 q5 · · · Q6 L L L L · · · L q6 q6 q6 q6 · · · Q7 L L L L · · · Q=d q7 q7 q7 q7 · · · Addressable Latch Store (do nothing) Demultiplex (active-High decoder when D H) D=H) OPERATING MODE MODE Master Reset
L d H H H q0 q1 q2 q3 q4 q5 q6 Q=d High voltage level Low voltage level Don't care High or Low data one setup time prior to the Low-to-High Enable transition Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
1989 Apr 11
3
|
|
