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Details, datasheet, quote on part number:N74F657N
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INTEGRATED CIRCUITS
74F657 Octal transceiver with 8-bit parity generator/checker
Product data Supersedes data of 1990 Jul 30 2003 Feb 04
Philips Semiconductors
Philips Semiconductors
Product data
Octal transceiver with 8-bit parity generator/checker
74F657
FEATURES
· Combines 74F245 and 74F280A functions in one package · High impedance base input for reduced loading (70 µA in HIGH
and LOW states)
The parity (PARITY) pin is an output from the generator/checker when transmitting from the port A to B (T/R = HIGH) and an input when receiving from port B to A port ( T/R = LOW). When transmitting (T/R = HIGH) the parity select (ODD/EVEN) input is set, then the A port data is polled to determined the number of high bits. The parity (PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number of high bits on port A. For example, if the parity select (ODD/EVEN) is set LOW (even parity), and the number of high bits on port A is odd, then the parity (PARITY) output will be HIGH, transmitting even parity. If the number of high bits on port A is even, then the parity (PARITY) output will be LOW, keeping even parity. When in receive mode (T/R = LOW) the B port is polled to determine the number of high bits. If parity select (ODD/EVEN) is LOW (even parity) and the number of highs on port B is: (1) odd and the parity (PARITY) input is HIGH, then ERROR will be HIGH, significantly no error. (2) even and the parity (PARITY) input is HIGH, then ERROR will be asserted LOW, indicating an error. TYPE TYPICAL PROPAGATION DELAY 8.0ns TYPICAL SUPPLY CURRENT (TOTAL) 100 mA
· Ideal in applications where high output drive and light bus loading · 3-state buffer outputs sink 64 mA and source 15 mA · Input diodes for termination effects · 24-pin plastic slim DIP (300 mil) package · Industrial temperature range available (40 °C to +85 °C)
DESCRIPTION
The 74F657 is an octal transceiver featuring non-inverting buffers with 3-state outputs and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A ports and 64 mA at the B ports. The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from A ports to B ports; receive (active LOW) enables data from B ports to A ports. The output enable (OE) input disables both the A and B ports by placing them in a high impedance condition when the OE input is HIGH. The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems. are required (IIL is 70 µA versus FAST std of 600 µA)
74F657
ORDERING INFORMATION
ORDER CODE COMMERCIAL RANGE DESCRIPTION 24-pin plastic slim DIP (300 mil) 24-pin plastic SOL VCC = 5 V ±10%, Tamb = 0 °C to +70 °C N74F657N N74F657D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = 40 °C to +85 °C I74F657N I74F657D PKG DWG # SOT222-1 SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS A0A7 B0B7 PARITY T/R ODD/EVEN OE A0A7 B0B7 PARITY ERROR A ports 3state inputs B ports 3state inputs Parity input Transmit/receive input Parity select input Output enable input (active LOW) A ports 3state outputs B ports 3state outputs Parity output Error output DESCRIPTION 74F (U.L.) HIGH / LOW 3.5 / 0.117 3.5 / 0.117 3.5 / 0.117 2.0 / 0.066 1.0 / 0.033 2.0 / 0.066 150 / 40 750 / 106.7 750 / 106.7 750 / 106.7 LOAD VALUE HIGH / LOW 70 µA / 70 µA 70 µA / 70 µA 70 µA / 70 µA 40 µA / 40 µA 20 µA / 20 µA 40 µA / 40 µA 3.0 mA / 24 mA 15 mA / 64 mA 15 mA / 64 mA 15 mA / 64 mA
NOTE: 1. One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
2003 Feb 04
2
853 1117 00081
Philips Semiconductors
Product data
Octal transceiver with 8-bit parity generator/checker
74F657
PIN CONFIGURATION
T/R 1 24 OE 23 B0 22 B1 21 B2 20 B3 19 GND 18 GND 17 B4 16 B5
LOGIC SYMBOL
A0 2 A1 3 A2 4 A3 5 A4 6 VCC 7 A5 8 A6 9 A7 10 ODD/EVEN 11 ERROR 12
2
3
4
5
6
8
9
10
A0 A1 A2 A3 A4 A5 A6 A7 1 24 11 T/R OE ODD/EVEN ERROR 12 PARITY 13
B0 B1 B2 B3 B4 B5 B6 B7
23 15 B6 14 B7 13 PARITY VCC = Pin 7 GND = Pin 18, 19
22
21
20
17
16
15
14
SF00414
SF00415
IEC/IEEE SYMBOL
24 1 11 2 G3 3 EN1/3G5 (REC) 3 EN2 (XMIT) N4 1 Z11 3 4 5 6 8 9 10 11 . . . 18 2k 4, 2 5 4, 1 12 13 2 22 21 20 17 16 15 14 23
SF00416
2003 Feb 04
3
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