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Details, datasheet, quote on part number:N74F712AD
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Datasheet text preview:
INTEGRATED CIRCUITS
74F711A, 74F711-1, 74F712A, 74F712-1 Multiplexers
Product specification IC15 Data Handbook 1990 Dec 13
Philips Semiconductors
Philips Semiconductors
Product specification
Multiplexers
74F711A 74F711-1 74F712A 74F712-1
74F711A/74F7111/ 74F712A/74F7121
Quint 2-to-1 Data Selector Multiplexer (3-State) Quint 2-to-1 Data Selector Multiplexer with 30W Equivalent Output Termination Impedance (3-State) Quint 3-to-1 Data Selector Multiplexer Quint 3-to-1 Data Selector Multiplexer with 30W Equivalent Output Termination Impedance
To improve speed and noise immunity, VCC and GND side pins are used. The 74F712A/74F712-1 consist of five 3-to1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F712A has two select (S0, S1) inputs to determine which set of five inputs will be propagated to the five outputs. The outputs source 15mA and sink 64mA. The 74F712-1 is the same as the 74F712A except that it has a 30W termination impedance on each output to reduce line noise and the outputs sink 5mA. TYPICAL SUPPLY CURRENT (TOTAL) 30mA 29mA 25mA 25mA
FEATURES for 74F711A/74F711-1
· Consists of five 2-to-1 Multiplexers · High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
· Designed for address multiplexing of dynamic RAM and other
applications
· Output inverting/non-inverting option · 30W termination impedance on each output 74F711-1 · Outputs sink 64mA (74F711A only)
FEATURES for 74F712A/74F712-1
TYPE 74F711A 74F711-1 74F712A 74F712-1
TYPICAL PROPAGATION DELAY 6.0ns 6.5ns 6.5ns 6.5ns
· Consists of five 3-to-1 Multiplexers · High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
· Designed for address multiplexing of dynamic RAM and other
applications
· 30W termination impedance on each output 74F712-1 · Outputs sink 64mA (74F712A only)
DESCRIPTION
The 74F711A/74F711-1 consist of five 2-to-1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F711A has a common select (S) input, an Output Enable (OE) input and an Output Inverting (INV) input to control the 3-State outputs. The outputs source 15mA and sink 64mA. The 74F711-1 is the same as the 74F711A except that is has a 30W termination impedance on each output to reduce line noise and the 3-State outputs sink 5mA. When the inverting input (INV) is Low, the input data path is inverted.
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 24-Pin Plastic Slim DIP (300 mil) 20-Pin Plastic SOL 24-Pin Plastic SOL COMMERCIAL RANGE VCC = 5V ± 10% Tamb = 0° C to +70°C N74F711AN, N74F711-1N N74F712AN, N74F712-1N N74F711AD, N74F711-1D N74F712AD, N74F712-1D PKG DWG # SOT146-1 SOT222-1 SOT163-1 SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS Dna, Dnb S 74F711A/ 74F711-1 OE INV Q0 - Q4 Q0 - Q4 Dna, Dnb, Dnc 74F712A/ 74F712-1 S0, S1 Q0 - Q4 Q0 - Q4 Data inputs Select input Output Enable input (active Low) Output inverting input (active Low) Data outputs for 74F711A Data outputs for 74F711-1 Data inputs Select inputs Data outputs for 74F712A Data outputs for 74F712-1 DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.066 1.0/0.033 1.0/0.033 1.0/0.033 750/106.7 750/8.33 1.0/0.066 1.0/0.033 750/106.7 750/8.33 LOAD VALUE HIGH/LOW 20µA/40µA 20µA/20µA 20µA/20µA 20µA/20µA 15mA/64mA 15mA/5mA 20µA/40µA 20µA/20µA 15mA/64mA 15mA/5mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
1990 Dec 13
2
853-1368 01258
Philips Semiconductors
Product specification
Multiplexers
74F711A/74F7111/ 74F712A/74F7121
PIN CONFIGURATION 74F711A/74F711-1
D0a D0b Q0 Q1 GND Q2 Q3 Q4 S 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 D1a D1b D2a D2b VCC D3a D3b D4a D4b OE
PIN CONFIGURATION 74F712A/74F712-1
S0 S1 Q0 Q1 Q2 GND Q3 Q4 D0c 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 D0a D1a D2a D3a D4a VCC D0b D1b D2b D3b D4b D4c
INV 10
D1c 10 D2c 11
SF01215
D3c 12
SF01216
LOGIC SYMBOL 74F711A/74F711-1
1 2 20 19 18 17 15 14 13 12
LOGIC SYMBOL 74F712A/74F712-1
24 18 9 23 17 10 22 16 11 21 15 12 20 14 13
D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b 9 10 11 S OE INV Q0 Q1 Q2 Q3 Q4 1 2
D0a D0b D0c D1a D1b D1c D2a D2b D2c D3a D3b D3c D4a D4b D4c
S0 S1 Q0 Q1 Q2 Q3 Q4
3 VCC = Pin 16 GND = Pin 5
4
6
7
8
3
4
5
7
8
SF01217
VCC = Pin 19 GND = Pin 6
SF01218
LOGIC SYMBOL (IEEE/IEC) 74F711A/74F711-1
MUX 1 11 10 1 2 20 19 18 17 15 14 13 12 8 7 6 4 1 3 G EN1 M
LOGIC SYMBOL (IEEE/IEC) 74F712A/74F712-1
MUX 1 2 G1 G2
24 18 9 23 17 10 22 16 11 21 15 12 20 14 13
3
4
5
7
8
SF01219
SF01220
1990 Dec 13
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