|Category||Communication => Freq/Signal Converters/Generators|
|Description||NE568A;SA568A; 150MHz Phase-locked Loop|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download NE568A datasheet
The is a monolithic phase-locked loop (PLL) which operates from 1Hz to frequencies in excess of 150MHz and features an extended supply voltage range and a lower temperature coefficient of the VCO center frequency in comparison with its predecessor, the NE 568. The NE568A is function and pin-compatible with the NE568, requiring only minor changes in peripheral circuitry (see Figure 3). Temperature compensation network is different, no resistor on Pin 12, needs to be grounded and Pin 13 has a 3.9k resistor to ground. Timing cap, C2, is different and for 70MHz operation with temperature compensation network should be 16pF, not 34pF as was used in the NE568. The NE568A has the following improvements: ESD protected; extended VCC range from to 5.5V; operating temperature range to 125°C (see Signetics Military 568A data sheet); less layout sensitivity; and lower TC of VCO (center frequency). The integrated circuit consists of a limiting amplifier, a current-controlled oscillator (ICO), a phase detector, a level shift circuit, V/I and I/V converters, an output buffer, and bias circuitry with temperature and frequency compensating characteristics. The design of the NE568A is particularly well-suited for demodulation of FM signals with extremely large deviation in systems which require a highly linear output. In satellite receiver applications with a 70MHz IF, the NE568A will demodulate ±20% deviations with less than 1.0% typical non-linearity. In addition to high linearity, the circuit has a loop filter which can be configured with series or shunt elements to optimize loop dynamic performance. The NE568A is available in 20-pin dual in-line and 20-pin SO (surface mounted) plastic packages.
Series or shunt loop filter component capability External loop gain control Temperature compensated ESD protected1APPLICATIONS
DESCRIPTION 20-Pin Plastic Small Outline Large (SOL) Package 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Plastic Small Outline Large (SOL) Package 20-Pin Plastic Dual In-Line Package (DIP)Satellite receivers Fiber optic video links VHF FSK demodulators Clock Recovery
LEVEL SHIFT V/I CONVERTER PHASE DETECTOR I/V CONVERTER AMP
NOTE: Pins 4 and 5 can tolerate 1000V only, and all other pins, greater than 2000V for ESD (human body model).
SYMBOL VCC TJ TSTG PDMAX JA Supply voltage Junction temperature Storage temperature range Maximum power dissipation Thermal resistance PARAMETER RATING 400 80 UNITS °C mW °C/W
The elctrical characteristics listed below are actual tests (unless otherwise stated) performed on each device with an automatic IC tester prior to shipment. Performance of the device in automated test set-up is not necessarily optimum. The NE568A is
layout-sensitive. Evaluation of performance for correlation to the data sheet should be done with the circuit and layout of Figures 3, 4, and 5 with the evaluation unit soldered in place. (Do not use a socket!)
VCC = 70MHz, Test Circuit Figure 3, fIN = 3.9k, unless otherwise specified. LIMITS SYMBOL VCC ICC PARAMETER Supply voltage Supply current TEST CONDITIONS MIN 4.5 NE/SA568A TYP 5 54 MAX V mA UNITS
LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN fOSC Maximum oscillator operating frequency3 Input signal level BW Demodulated bandwidth Non-linearity5 Lock range2 Dev = ±20%, Input = -20dBm Input = -20dBm Input = -20dBm Figure 1 6 Dev of fO measured at Pin 14 VIN -20dBm (30% AM) referred to ±20% deviation Centered (C2 + CSTRAY fO/7 NE/SA568A TYP MAX MHz mVP-P dBm MHz of fO ppm/°C k VP-P dB UNITSInput resistance4 Output impedance Demodulated VOUT AM rejection Distribution6 Drift with supply
NOTE: 1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance. 2. Limits are set symmetrical to fO. Actual characteristics may have asymmetry beyond the specified limits. 3. Not 100% tested, but guaranteed by design. 4. Input impedance depends on package and layout capacitances. See Figures 6 and 5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (VOUT). Non-linearity is then calculated from a straight line over the deviation range specified. 6. Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied.
The is a high-performance phase-locked loop (PLL). The circuit consists of conventional PLL elements, with special circuitry for linearized demodulated output, and high-frequency performance. The process used has NPN transistors with > 6GHz. The high gain and bandwidth of these transistors make careful attention to layout and bypass critical for optimum performance. The performance of the PLL cannot be evaluated independent of the layout. The use of the application layout in this data sheet and surface-mount capacitors are highly recommended as a starting point. The input to the PLL is through a limiting amplifier with a gain of 200. The input of this amplifier is differential (Pins 10 and 11). For single-ended applications, the input must be coupled through a DC-blocking capacitor with low impedance at the frequency of interest. The single-ended input is normally applied to Pin 11 with Pin 10 AC-bypassed with a low-impedance capacitor. The input impedance is characteristically slightly above 500. Impedance match is not necessary, but loading the signal source should be avoided. When the source 75, a DC-blocking capacitor is usually all that is needed. Input amplification is low enough to assure reasonable response time in the case of large signals, but high enough for good AM rejection. After amplification, the input signal drives one port of a multiplier-cell phase detector. The other port is driven by the current-controlled oscillator (ICO). The output of the phase comparator is a voltage proportional to the phase difference of the input and ICO signals. The error signal is filtered with a low-pass filter to provide a DC-correction voltage, and this voltage is converted to a current which is applied to the ICO, shifting the frequency in the direction which causes the input and ICO to have a 90° phase relationship. The oscillator is a current-controlled multivibrator. The current control affects the charge/discharge rate of the timing capacitor. It is common for this type of oscillator to be referred as a
voltage-controlled oscillator (VCO), because the output of the phase comparator and the loop filter is a voltage. To control the frequency of an integrated ICO multivibrator, the control signal must be conditioned by a voltage-to-current converter. In the NE568A, special circuitry predistorts the control signal to make the change in frequency a linear function over a large control-current range. The free-running frequency of the oscillator depends on the value of the timing capacitor connected between Pins 4 and 5. The value of the timing capacitor depends on internal resistive components and current sources. When = 1.2k and 0, a very close approximation of the correct capacitor value is: F fO where STRAY The temperature-compensation resistor, R4, affects the actual value of capacitance. This equation is normalized to 70MHz. See 10 for correction factors. The loop filter determines the dynamic characteristics of the loop. In most PLLs, the phase detector outputs are internally connected to the ICO inputs. The NE568A was designed with filter output to input connections from Pins 20 ( DET) to 17 (ICO), and Pins 19 ( DET) to 18 (ICO) external. This allows the use of both series and shunt loop-filter elements. The loop constratints are: + 0.12VRadian (Phase Detector Constant) K O Radians (ICO Constant) 70MHz V sec
The loop filter determines the general characteristics of the loop. Capacitors C9, C10, and resistor R1, control the transient output of the phase detector. Capacitor C9 suppresses 70MHz feedthrough by interaction with 100 load resistors internal to the phase detector.
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