The OM5232 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The OM5232 has the same instruction set as the 80C51. See also: OM5202 ROMless version OM5234 16K bytes mask programmable ROM OM5238 32K bytes mask programmable ROM This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The OM5232 contains a non-volatile × 8 read-only program memory, a volatile × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the OM5232 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75µs and in 1.5µs. Multiply and divide instructions require 3µs.
· 80C51 central processing unit· × 8 ROM, expandable externally to 64k bytes· × 8 RAM, expandable externally to 64k bytes· Two standard 16-bit timer/counters· Four 8-bit I/O ports· Two open drain I/O's (P1.6, P1.7)· Full-duplex UART facilities· Power control modes
· ROM code protection· Extended frequency range: to 16 MHz· Operating ambient temperature range: 0 to
PHILIPS PART ORDER NUMBER PART MARKING OM5232/FBP/xxx 1)
TEMPERATURE RANGE °C, PACKAGE to +70, Plastic Dual Inline Package, 40 leads to +70, Plastic Quad Flat Pack, 44 leads
Details are as specified by the data sheet for the equivalent type: = P80C652 without I2C function. = P83C652 without I2C function. = P83C654 without I2C function. = P83C528 without I2C function.
NOTE: 1. Due to EMC improvements, all VSS pins must be connected to VSS.
PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT
PIN NUMBER MNEMONIC VSS VDD P0.00.7 DIP 40 3932 QFP TYPE I I/O NAME AND FUNCTION Ground: 0V reference. With the QFP package all VSS pins to VSS4) must be connected. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions include: open drain output open drain output Port 2: Port an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: Read strobe to external program memory via Port 0 and Port It is activated twice each machine cycle during fetches from the external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs without external pullups. External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 16384. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VDD 0.5V or VSS 0.5V, respectively.