|Description||Stb5860 Set-top Box STB Concept|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download OM5730 datasheet
Preliminary specification File under Integrated Circuits, IC02 1999 Aug 25
CONTENTS FEATURES SAA7219 features General SAA7219 features MPEG2 systems features External interface features SAA7215 family features General SAA7215 family features CPU related features MPEG2 system features MPEG2 video features MPEG2 audio features Graphics features GENERAL DESCRIPTION Introduction Reference design goal Benefits Key system benefits Key IC benefits BLOCK DIAGRAMS HARDWARE IC list Main board SAA7219 SAA7215 Front-end Front panel LNB interface IR Keys SCART control Memory Non-Volatile Memory (NVM) DRAM Boot ROM Flash Video and graphics RAM Memory options Connectors SOFTWARE DESCRIPTION Software overview General software resources Application layer System control layer Platform layer I/O device drivers General software resources System control layer Platform layer Application layer Top level menu Installation menu Tuning menu Feature demonstration menu
DEVELOPMENT ENVIRONMENT Summary of the STB5860 kit The hardware The software Documentation Test reports How to get started Hardware interface with the STB5860 Software interface with the STB5860 Running `hello world' CONTENTS LIST FOR STB5860 DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
Internal PR3930 32-bit RISC processor running at 81 MHz Comprehensive driver software and development tool support A JTAG interface for board test support 8-kbyte 8-way set associative instruction cache 4-kbyte 4-way set associative instruction cache. 1.1.2 MPEG2 SYSTEMS FEATURES 1.1.3 EXTERNAL INTERFACE FEATURES A 32-bit microcontroller extension bus supporting DRAM, SDRAM flash, (E)PROM and external memory mapped I/O devices. It also supports a synchronous interface to communicate with the integrated MPEG Audio Video Graphics (AVG) decoder SAA7215 family at 40.5 Mbytes/s. An IEEE 1284 interface supporting master and slave modes; usable as a general purpose port 2 UART (RS232) data ports with DMA capabilities (187.5 kbits/s) including hardware flow control RXD, TXD, RTS and CTS for modem support Two dedicated smart card reader interfaces (ISO 7816 compatible) with DMA capabilities Two I2C-bus master/slave transceivers supporting the standard (100 kbits/s) and fast (400 kbits/s) I2C-bus modes 32 general purpose, bidirectional I/O interface pins, 8 of which may also be used as interrupt inputs 2 Pulse Width Modulated (PWM) outputs with 8-bit resolution. 1.2.1 SAA7215 family features GENERAL SAA7215 FAMILY FEATURES
Parsing of Transport Stream (TS), Philips Semiconductors hardware and proprietary software data streams; maximum input rate is 108 Mbits/s A real time descrambler consisting of 3 modules: A control word bank containing 14 pairs (odd and even) of control words and a default control word The Digital Video Broadcasting (DVB) descrambler core implementing the stream decipher and block decipher algorithms The MULTI2 descrambler algorithm implementing the CBC and OFB mode descrambling functions. Hardware section filtering based on 32 different Packet Identifiers (PIDs) with a flexible number of filter conditions or 4-byte condition plus or 4-byte mask) per PID and a total filter capacity 40 (8-byte condition checks) 80 (4-byte condition checks) filter conditions 4 Transport Stream/Packetized Elementary Stream (PES) filters for retrieval of data TS or PES level for applications such as subtitling, TXT or retrieval of private data Flexible Direct Memory Access (DMA) based storage of the 32 section substreams and 4 TS/PES data substreams in the external memory System time base management with a double counter mechanism for clock control and discontinuity handling 2 Presentation Time Stamp (PTS)/Decoding Time Stamp (DTS) timers A General Purpose/High speed (GP/HS) filter which can serve as alternative input from e.g. IEEE 1394 devices. It can also output either scrambled or descrambled TS to IEEE 1394 devices.
Single or double external synchronous DRAM organized × 16 interfacing at 81 MHz. Due to efficient memory use in MPEG decoding, more than 1 Mbit is available for graphics in the single SDRAM configuration whereas 17 Mbits are available in the double SDRAM configuration targeted to BSkyB 3.00 and Canal+ 4.0 specifications. Dedicated input for compressed audio and video in PES ES in byte wide or bit serial format; accompanying strobe signals distinguish between audio and video data Optimum compatibility with SAA7219 TMIPS controller Flexible memory allocation under control of the external Central Processing Unit (CPU) enables optimized partitioning of memory for different tasks Boundary scan testing implemented.
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