|
Details, datasheet, quote on part number:P51XAG33KFBD
| |
Datasheet text preview:
INTEGRATED CIRCUITS
XA-G3 XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification Supersedes data of 1998 Aug 14 IC25 Data Handbook 1999 Apr 07
Philips Semiconductors
Philips Semiconductors
Product specification
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
XA-G3
FAMILY DESCRIPTION
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for high-volume, low-cost applications. The XA family provides an upward compatibility path for 80C51 users who need higher performance and 64k or more of program memory. Existing 80C51 code can also easily be translated to run on XA microcontrollers. The performance of the XA architecture supports the comprehensive bit-oriented operations of the 80C51 while incorporating support for multi-tasking operating systems and high-level languages such as C. The speed of the XA architecture, at 10 to 100 times that of the 80C51, gives designers an easy path to truly high performance embedded control. The XA architecture supports:
· Instruction set tailored for high level language support · Multi-tasking and real-time executives that include up to 32
vectored interrupts, 16 software traps, segmented data memory, and banked registers to support context switching
· Low power operation, which is intrinsic to the XA architecture,
includes power-down and idle modes. More detailed information on the core is available in the XA User Guide.
SPECIFIC FEATURES OF THE XA-G3
· 20-bit address range, 1 megabyte each program and data space.
(Note that the XA architecture supports up to 24 bit addresses.)
· Upward compatibility with the 80C51 architecture · 16-bit fully static CPU with a 24-bit program and data address
range
· 2.7V to 5.5V operation · 32K bytes on-chip EPROM/ROM program memory =
XA-G37/XA-G33
· Eight 16-bit CPU registers each capable of performing all
arithmetic and logic operations as well as acting as memory pointers. Operations may also be performed directly to memory.
· 512 bytes of on-chip data RAM · Three counter/timers with enhanced features
(equivalent to 80C51 T0, T1, and T2)
· Both 8-bit and 16-bit CPU registers, each capable of performing
all arithmetic and logic operations.
· An enhanced instruction set that includes bit intensive logic
operations and fast signed or unsigned 16 × 16 multiply and 32 / 16 divide
· Watchdog timer · Two enhanced UARTs · Four 8-bit I/O ports with 4 programmable output configurations · 44-pin PLCC and 44-pin LQFP packages
ORDERING INFORMATION
ROMless P51XAG30KB BD P51XAG30KB A P51XAG30KF BD P51XAG30KF A ROM P51XAG33KB BD P51XAG33KB A P51XAG33KF BD P51XAG33KF A EPROM1 PXAG37KB BD PXAG37KB A PXAG37KF BD PXAG37KF A OTP OTP OTP OTP TEMPERATURE RANGE °C AND PACKAGE 0 to +70, Plastic Low Profile Quad Flat Pkg. 0 to +70, Plastic Leaded Chip Carrier 40 to +85, Plastic Low Profile Quad Flat Pkg. 40 to +85, Plastic Leaded Chip Carrier FREQ (MHz) 30 30 30 30 DRAWING NUMBER SOT3891 SOT1872 SOT3891 SOT1872
NOTE: 1. OTP = One Time Programmable EPROM. UV = Erasable EPROM.
1999 Apr 07
2
853-2052 21197
Philips Semiconductors
Product specification
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
XA-G3
PIN CONFIGURATIONS 44-Pin PLCC Package
6 1 40
44-Pin LQFP Package
44 34
7
39 1 PLCC 33
LQFP
17
29
11
23
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function V SS P1.0/A0/WRH P1.1/A1 P1.2/A2 P1.3/A3 P1.4/RxD1 P1.5/TxD1 P1.6/T2 P1.7/T2EX RST P3.0/RxD0 NC P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/BUSW P3.6/WRL P3.7/RD XTAL2 XTAL1 V SS Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
28 Function VDD P2.0/A12D8 P2.1/A13D9 P2.2/A14D10 P2.3/A15D11 P2.4/A16D12 P2.5/A17D13 P2.6/A18D14 P2.7/A19D15 PSEN ALE/PROG NC EA/VPP/WAIT P0.7/A11D7 P0.6/A10D6 P0.5/A9D5 P0.4/A8D4 P0.3/A7D3 P0.2/A6D2 P0.1/A5D1 P0.0/A4D0 VDD SU00525 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5/TxD1 P1.6/T2 P1.7/T2EX RST P3.0/RxD0 NC P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/BUSW P3.6/WRL P3.7/RD XTAL2 XTAL1 V SS VDD P2.0/A12D8 P2.1/A13D9 P2.2/A14D10 P2.3/A15D11 P2.4/A16/D12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 Function P2.5/A17D13 P2.6/A18D14 P2.7/A19D15 PSEN ALE/PROG NC EA/VPP/WAIT P0.7/A11D7 P0.6/A10D6 P0.5/A9D5 P0.4/A8D4 P0.3/A7D3 P0.2/A6D2 P0.1/A5D1 P0.0/A4D0 VDD V SS P1.0/A0/WRH P1.1/A1 P1.2/A2 P1.3/A3 P1.4/RxD1 SU00580
LOGIC SYMBOL
VDD V SS
XTAL1 T2EX* T2* TXD1 RXD1 A3 A2 A1 A0/WRH ADDRESS BUS
XTAL2
RST EA/WAIT PSEN ADDRESS AND DATA BUS ALE PORT 2 PORT 0
ALTERNATE FUNCTIONS
RxD0 TxD0 INT0 INT1 T0 T1/BUSW WRL RD
*
NOT AVAILABLE ON 40-PIN DIP PACKAGE
PORT 3
PORT 1
SU00526
1999 Apr 07
3
|
|
