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Details, datasheet, quote on part number:P83C528FBA
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Datasheet text preview:
INTEGRATED CIRCUITS
80C528/83C528 CMOS single-chip 8-bit microcontroller
Product specification IC20 Data Handbook 1995 Feb 02
Philips Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
DESCRIPTION
The 8XC528 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC528 has the same instruction set as the 80C51. Three versions of the derivative exist: ROM
multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and I2C-bus), and on-chip oscillator and timing circuits. In addition, the 8XC528 has two software selectable modes of power reduction -- idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
FEATURES
· 80C51 instruction set
32k × 8 ROM (83C528) ROMless (80C528) 512 × 8 RAM Memory addressing capability 64k ROM and 64k RAM Three 16-bit counter/timers On-chip watchdog timer with oscillator Full duplex UART I2C serial interface Four 8-bit I/O ports
· 83C528 -- 32k bytes mask programmable · 80C528 -- ROMless version of the
83C528
· 87C528 -- 32k bytes EPROM (described
in a separate data sheet) This device provides architectural enhancements that make it applicable in a variety of applications in consumer, telecom and general control systems, especially in those systems which need large ROM and RAM capacity on-chip. The 8XC528 contains a 32k × 8 ROM (83C528), a 512 × 8 RAM, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a watchdog timer with a separate oscillator, a
· Power control modes:
Idle mode Power-down mode Warm start from power-down
· CMOS and TTL compatible · Extended temperature ranges · ROM code protection · 7-source and 7-vector interrupt structure · Up to 3 external interrupt request inputs · Two programmable power reduction modes · Termination of Idle mode by any interrupt, · XTAL frequency range: 1.2 MHz to 16 MHz
external or WDT (watchdog) reset (Idle and Power-down) with 2 priority levels
PIN CONFIGURATIONS
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 SDA/P1.7 RST 1 2 3 4 5 6 7 8 9 DUAL IN-LINE PACKAGE 40 VDD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 SDA/P1.7 RST 1 2 3 4 5 6 7 8 9 SHRINK DUAL IN-LINE PACKAGE 42 VDD 41 P0.0/AD0 40 P0.1/AD1 7 39 P0.2/AD2 38 P0.3/AD3 37 P0.4/AD4 36 P0.5/AD5 35 P0.6/AD6 34 P0.7/AD7 33 EA 32 NC* 31 ALE 30 PSEN 29 P2.7/A15 28 P2.6/A14 27 P2.5/A13 26 P2.4/A12 25 P2.3/A11 24 P2.2/A10 23 P2.1/A9 22 P2.0/A8 12 22 11 1 QUAD FLAT PACK 23 33 44 34 18 28 17 LEADED CHIP CARRIER 29 39 6 1 40
RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20
RxD/P3.0 10 NC* 11
TxD/P3.1 12 INT0/P3.2 13 INT1/P3.3 14 T0/P3.4 15 T1/P3.5 16 WR/P3.6 17 RD/P3.7 18 XTAL2 19 XTAL1 20 VSS 21
* DO NOT CONNECT
1995 Feb 02
2
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39
1
33
PLCC
PQFP
17
29
11
23
18
28
12 Function NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7RD XTAL2 XTAL1 V SS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
22 Function P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Function NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 V SS
Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
* DO NOT CONNECT
* DO NOT CONNECT
LOGIC SYMBOL
VDD XTAL1 PORT 0 ADDRESS AND DATA BUS V SS
XTAL2 T2 T2EX RST EA PSEN SECONDARY FUNCTIONS ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 1
SCL SDA
PORT 3
PORT 2
ADDRESS BUS
1995 Feb 02
3
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