Details, datasheet, quote on part number: P8xC591VFx
DescriptionP8XC591; Single-chip 8-bit Microcontroller With CAN Controller
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload P8xC591VFx datasheet


Features, Applications

Preliminary Specification File under Integrated Circuits, IC28 2000 Jul 26

CONTENTS FEATURES 80C51 Related Features of the 8xC591 CAN Related Features of the 8xC591 GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning diagram Pin description MEMORY ORGANIZATION Program Memory Addressing Expanded Data RAM addressing Dual DPTR I/O FACILITIES OSCILLATOR CHARACTERISTICS RESET LOW POWER MODES Stop Clock Mode Idle Mode Power-down Mode CAN, CONTROLLER AREA NETWORK Features of the PeliCAN controller PeliCAN structure Communication between PeliCAN controller and CPU Register and Message Buffer description CAN Registers SERIAL I/O SIO0 STANDARD SERIAL INTERFACE UART Multiprocessor Communications Serial Port Control Register Baud Rate Generation More about UART Modes Enhanced UART SIO1, I2C SERIAL IO Modes of Operation SIO1 Implementation and Operation Software Examples of SIO1 Service Routines TIMER 2 Features of Timer WATCHDOG TIMER (T3)

PULSE WIDTH MODULATED OUTPUTS Prescaler Frequency Control Register (PWMP) Pulse Width Register 0 (PWM0) Pulse Width Register 1 (PWM1) PORT 1 OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) ADC features ADC functional description 10-Bit Analog-to-Digital Conversion 10-Bit ADC Resolution and Analog Supply Power Reduction Modes INTERRUPTS Interrupt Enable Registers Interrupt Enable and Priority Registers Interrupt priority Interrupt Vectors INSTRUCTION SET Addressing Modes LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS Timing symbol definitions EPROM CHARACTERISTICS Program verification Security bits PACKAGE OUTLINES SOLDERING Plastic leaded-chip carriers/quad flat-packs DEFINITIONS LIFE SUPPORT APPLICATIONS

Full static 80C51 Central Processing Unit available as OTP, ROM and ROMless 16 Kbytes internal Program Memory expandable externally to 64 Kbytes 512 bytes on-chip Data RAM expandable externally to 64 Kbytes Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture & compare) 10-bit ADC with 6 multiplexed analog inputs with fast 8-bit ADC option Two 8-bit resolution, Pulse Width Modulated outputs 32 I/O port pins in the standard 80C51 pinout I2C-bus serial I/O port with byte oriented master and slave functions On-chip Watchdog Timer T3 Extended temperature range: to +85C Accelerated (prescaler 1:1) instruction cycle time @ 12 MHz Operation voltage range: 5% Security bits: ROM version has 2 bits OTP/EPROM version has 3 bits 32 bytes Encryption array 4 level priority interrupt, 15 interrupt sources Full-duplex enhanced UART with programmable Baudrate Generator Power Control Modes: Clock can be stopped and resumed Idle Mode Power-down Mode ADC active in Idle Mode Second DPTR register ALE inhibit for EMI reduction Programmable I/O port pins (pseudo bi-directional, push-pull, high impedance, open drain) Wake-up from Power-down by external interrupts Software reset bit (AUXR1.5) Low active reset pin Power-on detect reset Once mode

CAN 2.0B active controller, supporting 11-bit Standard and 29-bit Extended indentifiers 1 Mbit/s CAN bus speed with 8 MHz clock achievable 64 byte receive FIFO (can capture sequential Data Frames from the same source as required by the Transport Layer of higher protocols such as DeviceNet, CANopen and OSEK) 13 byte transmit buffer Enhanced PeliCAN core (from the SJA1000 stand-alone CAN2.0B controller) 1.2.1 PELICAN FEATURES

Four independently configurable Screeners (Acceptance Filters) Each Screener has two 32-bit specifies: 32-bit Match and 32-bit Mask 32-bits of Mask per Screener allows unique Group addressing per Screener Higher layer protocols especially supported in Standard CAN format with: Up to four, 11-bit ID Screeners that also Screen the two (2) Data Bytes i.e., Data Frames are Screened by the CAN ID and by Data Byte content Up to eight, 11-bit ID Screeners half of which also Screen the first Data Byte All Screeners are changeable "on the fly" Listen Only Mode, Self Test Mode Error Code Capture, Arbitration Lost Capture, readable Error Counters


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