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Part: PCA9541D/01
Category:
Interface and Interconnect
-> I2C
Description: 2-to-1 I2C Master Selector With Interrupt Logic And Reset<<<>>>the PCA9541 is a 2-to-1 i C Master Selector Designed For High Reliability Dual Master i C Applications Where System Operation is Required, Even When One Master Fails or The Controller Card is Removed For Maintenance. The Two Masters (e.g., Primary And Back-up) Are Located on Separate i C-buses That Connect to The Same Downstream i C-bus Slave Devices. I C Commands Are Sent BY Either i C-bus Master And Are Used to Select One Master at a Time. Either Master at Any Time CAN Gain Control of The Slave Devices if The Other Master is Disabled or Removed From The System. The Failed Master is ISOlated From The System And Will Not Affect Communication Between The On-line Master And The Slave Devices on The Downstream i C-bus. <<<>>><<<>>>Three Versions Are Offered For Different Architectures. PCA9541/01 With Channel 0 Selected at Start-up, PCA9541/02 With Channel 0 Selected After Start-up And After Stop Condition is Detected, And PCA9541/03 With no Channel Selected After Start-up. <<<>>><<<>>>The Interrupt Outputs Are Used to Provide an Indication of Which Master Has Control of The Bus. One Interrupt Input (INT_IN) Collects Downstream Information And Propagates it to The 2 Upstream i C-buses (INT0 And INT1) if Enabled. INT0 And INT1 Are Also Used to Let The Previous Bus Master Know That it is Not in Control of The Bus Anymore And to Indicate The Completion of The Bus Recovery/initialization Sequence. Those Interrupts CAN be Disabled And Will Not Generate an Interrupt if The Masking Option is Set. <<<>>><<<>>>A Bus Recovery/initialization if Enabled Sends Nine Clock Pulses, a Not Acknowledge, And a Stop Condition in Order to Set The Downstream i C-bus Devices to an Initialized State Before Actually Switching The Channel to The Selected Master. <<<>>><<<>>>An Interrupt is Sent to The Upstream Channel When The Recovery/initialization Procedure is Completed. <<<>>><<<>>>An Internal Bus Sensor Senses The Downstream i C Traffic And Generates an Interrupt if a Channel Switch Occurs During a Non-idle Bus Condition. This Function is Enabled When The PCA9541 Recovery/initialization is Not Used. The Interrupt Signal Informs The Master That an External i C-bus Recovery/initialization Needs to be Performed. It CAN be Disabled And an Interrupt Will Not be Generated. <<<>>><<<>>>The Pass Gates of The Switches Are Constructed Such That The VDD Pin CAN be Used to Limit The Maximum High Voltage, Which Will be Passed BY The PCA9541. This Allows The Use of Different Bus Voltages on Each Pair, so That 1.8 V 2.5 V or 3.3 V Devices CAN Communicate With 5 V Devices Without Any Additional Protection. <<<>>><<<>>>The PCA9541 Does Not ISOlate The Capacitive Loading on Either Side of The Device so The Designer Must Take Into Account All Trace And Device Capacitances on Both Sides of The Device, And Pull-up Resistors Must be Used on All Channels. <<<>>><<<>>>External Pull-up Resistors Pull The Bus to The Desired Voltage Level For Each Channel. All I/o Pins Are 6.0 V Tolerant. <<<>>><<<>>>An Active-low Reset Input Allows The PCA9541 to be Initialized. Pulling The Reset Pin Low Resets The i C State Machine And Configures The Device to Its Default State as Does The Internal Power on Reset Function. <<<>>><<<>>> <<<>>> Features 2-to-1 Bi-directional Master Selector <<<>>>I C Interface Logic; Compatible With Smbus Standards <<<>>>PCA9541/01 Powers-up With Channel 0 Selected <<<>>>PCA9541/02 Powers-up With Channel 0 Selected After Stop Condition Detected (bus Idle) on Channel 0 <<<>>>PCA9541/03 Powers-up With no Channel Selected And Either Master CAN Take Control of The Bus <<<>>>Active Low Interrupt Input <<<>>>2 Active Low Interrupt Outputs <<<>>>Active Low Reset Input <<<>>>4 Address Pins Allowing up to 16 Devices on The i C-bus <<<>>>Channel Selection Via i C-bus <<<>>>Bus Initialization/recovery Function <<<>>>Bus Traffic Sensor <<<>>>Low Rdson Switches <<<>>>Allows Voltage Level Translation Between 1.8 V, 2.5 V, 3.3 V And 5 V Buses <<<>>>No Glitch on Power-up <<<>>>Supports Hot Insertion <<<>>>Software Identical For Both Masters <<<>>>Low Stand-by Current <<<>>>Operating Power Supply Voltage Range of 2.3 V to 5.5 V <<<>>>6.0 V Tolerant Inputs <<<>>>0 to 400 KHZ Clock Frequency <<<>>>ESD Protection Exceeds 2000 V HBM Per JESD22-A114, 200 V MM Per JESD22-A115 And 1000 V CDM Per JESD22-C101 <<<>>>Latch-up Testing is Done to Jesdec Standard JESD78 Which Exceeds 100 ma <<<>>>Packages Offered: SO16, TSSOP16, HVQFN16
Company: Philips Semiconductors
Datasheet: Download PCA9541D/01 datasheet File size : 2565 kB
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INTEGRATED CIRCUITS
PCA9541 2-to-1 I2C master selector with interrupt logic and reset
Product data 2003 Dec 02
Philips Semiconductors
Philips Semiconductors
Product data
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
DESCRIPTION
The PCA9541 is a 2-to-1 I2C master selector designed for high reliability dual master I2C applications where system operation is required, even when one master fails or the controller card is removed for maintenance. The two masters (e.g., primary and back-up) are located on separate I2C-buses that connect to the same downstream I2C-bus slave devices. I2C commands are sent by either I2C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream I2C-bus. Three versions are offered for different architectures. PCA9541/01 with channel 0 selected at start-up, PCA9541/02 with channel 0 selected after start-up and after stop condition is detected, and PCA9541/03 with no channel selected after start-up. The interrupt outputs are used to provide an indication of which master has control of the bus. One interrupt input (INT_IN) collects downstream information and propagates it to the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a stop condition in order to set the downstream I2C-bus devices to an initialized state before actually switching the channel to the selected master. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. An internal bus sensor senses the downstream I2C traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. This function is enabled when the PCA9541 recovery/initialization is not used. The interrupt signal informs the master that an external I2C-bus recovery/initialization needs to be performed. It can be disabled and an interrupt will not be generated. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9541. This allows the use of different bus voltages on each pair, so that 1.8 V 2.5 V or 3.3 V devices can communicate with 5 V devices without any additional protection. The PCA9541 does not isolate the capacitive loading on either side of the device so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant. An active-LOW Reset Input allows the PCA9541 to be initialized. Pulling the RESET pin LOW resets the I2C state machine and configures the device to its default state as does the internal power on reset function.
FEATURES
· 2-to-1 bi-directional master selector · I2C interface logic; compatible with SMBus standards · PCA9541/01 powers-up with Channel 0 selected · PCA9541/02 powers-up with Channel 0 selected after STOP · PCA9541/03 powers-up with no channel selected and either · Active LOW Interrupt Input · 2 Active LOW Interrupt Outputs · Active LOW Reset Input · 4 address pins allowing up to 16 devices on the I2C-bus · Channel selection via I2C-bus · Bus initialization/recovery function · Bus traffic sensor · Low RdsON switches · Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and · No glitch on power-up · Supports hot insertion · Software identical for both masters · Low stand-by current · Operating power supply voltage range of 2.3 V to 5.5 V · 6.0 V tolerant Inputs · 0 to 400 kHz clock frequency · ESD protection exceeds 2000 V HBM per JESD22-A114, · Latch-up testing is done to JESDEC Standard JESD78 which · Packages offered: SO16, TSSOP16, HVQFN16
APPLICATIONS
exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 5 V buses master can take control of the bus condition detected (bus idle) on Channel 0
· High reliability systems with dual masters · Gatekeeper multiplexer on long single bus · Bus initialization/recovery for slave devices without hardware · Allows masters without arbitration logic to share resources
reset
2003 Dec 02
2
Philips Semiconductors
Product data
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN 16-Pin Plastic SO 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN 16-Pin Plastic SO 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN TEMPERATURE RANGE -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C ORDER CODE PCA9541D/01 PCA9541PW/01 PCA9541BS/01 PCA9541D/02 PCA9541PW/02 PCA9541BS/02 PCA9541D/03 PCA9541PW/03 PCA9541BS/03 TOPSIDE MARK PCA9541D/01 9541/01 41/1 PCA9541D/02 9541/02 41/2 PCA9541D/03 9541/03 41/3 DRAWING NUMBER SOT109-1 SOT403-1 SOT629-1 SOT109-1 SOT403-1 SOT629-1 SOT109-1 SOT403-1 SOT629-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
PIN CONFIGURATION
1 2 3 4 5 6 7 8 16 VDD 15 INT_IN 14 SDA_SLAVE 13 SCL_SLAVE 12 A3 11 A2 10 A1 9 A0 RESET 2 SCL_MST1 3 SDA_MST1 4 SW02008 6 7 5 8 11 SCL_SLAVE SCL_MST0 1 16 SDA_MST0
SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 V SS
13 INT_IN 12 SDA_SLAVE 10 A3 9 A2 A1
INT0
15 INT0 VSS
TOP VIEW
Figure 1. SO16/TSSOP16 pin configuration.
INT1
A0
14 VDD
SW02034
Figure 2. HVQFN16 pin configuration.
PIN DESCRIPTION
SO/TSSOP PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HVQFN PIN NUMBER 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS A0 A1 A2 A3 SCL_SLAVE SDA_SLAVE INT_IN VDD FUNCTION Active LOW interrupt output 0 (external pull-up required) Serial data master 0 (external pull-up required) Serial clock master 0 (external pull-up required) Active LOW reset input (external pull-up required) Serial clock master 1 (external pull-up required) Serial data master 1 (external pull-up required) Active LOW interrupt output 1 (external pull-up required) Supply ground Address input 0 (externally held to GND or VCC) Address input 1 (externally held to GND or VCC) Address input 2 (externally held to GND or VCC) Address input 3 (externally held to GND or VCC) Serial clock slave (external pull-up required) Serial data slave (external pull-up required) Active LOW interrupt input (external pull-up required) Supply voltage
2003 Dec 02
3
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