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Part: PDTC114T
Category:
Discrete
-> Transistors
-> Bipolar
-> RETs (Resistor Equipped transistors)
Description: PDIUSBP11A; Universal Serial Bus Transceiver;; Package: SOT23 (SST3), SOT323 (UMT3, CMPAK), SOT346 (SMT3, MPAK), SOT416 (EMT3, SMPAK), SOT54 (SPT, E-1)
Company: Philips Semiconductors
Datasheet: Download PDTC114T datasheet File size : 5 kB
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Datasheet text preview:
INTEGRATED CIRCUITS
PDIUSBP11A Universal Serial Bus Transceiver
Product data Supersedes data of 1999 Jun 04 2001 Jun 12
Philips Semiconductors
Philips Semiconductors
Product data
Universal Serial Bus transceiver
PDIUSBP11A
FEATURES
· Complies with Universal Serial Bus specification 1.1 · Utilizes digital inputs and outputs to transmit and receive USB
cable data
DESCRIPTION
The PDIUSBP11A is a one chip generic USB transceiver. It is designed to allow 5.0V or 3.3V programmable and standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of transmitting and receiving serial data at both full speed (12Mbit/s) and low speed (1.5Mbit/s) data rates. The pinout conforms with the "Serial Interface Engine". Implementation of the Serial Interface Engine along with the USB transceiver allows the designer to make USB compatible devices with off-the-shelf logic and easily modify and update the application. The PDIUSBP11A is backward compatible to the PDIUSBP11 and allows for single-ended data interfacing.
· Supports 12Mbit/s "Full Speed" and 1.5Mbit/s "Low Speed" serial
data transmission
· Compatible with the VHDL "Serial Interface Engine" from USB
Implementers' Forum
· Supports single-ended data interface · Single 3.3V supply · Available in SO-14, SSOP-14 and TSSOP-14 packages
ORDERING INFORMATION
TYPE NUMBER PACKAGE NAME PDIUSBP11AD PDIUSBP11ADB PDIUSBP11APW SO14 SSOP14 TSSOP14 DESCRIPTION
VERSION SOT108-1 SOT337-1 SOT402-1
plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm
PIN CONFIGURATION
MODE OE# RCV VP VM SUSPND GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V CC VMO/FSEO VPO D) D SPEED NC
FUNCTIONAL DIAGRAM
OE# SPEED VMO/FSEO VPO D D+
RCV
+
VP
SV00559
VM
SV00560
2001 Jun 12
2
853-2008 26486
Philips Semiconductors
Product data
Universal Serial Bus transceiver
PDIUSBP11A
PIN DESCRIPTION
PIN No. 3 2 1 PIN SYMBOL RCV OE# MODE I/O O I I NAME AND FUNCTION Receive data. CMOS level output for USB differential input Output Enable. Active LOW, enables the transceiver to transmit data on the bus. When not active the transceiver is in receive mode Mode. When left unconnected, a weak pull-up transistor pulls it to VCC and in this mode, the PDIUSBP11A is backward compatible to PDIUSBP11. When connected to GND, the VMO/FSEO pin takes the function of FSEO (Force SEO). Inputs to differential driver. (Outputs from SIE). MODE 0 VPO 0 0 1 1 0 0 1 1 VMO/FSEO 0 1 0 1 0 1 0 1 RESULT Logic "0" SE0# Logic "1" SEO# SE0# Logic "0" Logic "1" Illegal code
12, 13 13
VPO, VMO/FSEO
I 1
Gated version of D and D+. Outputs are logic "0" and logic "1". Used to detect single ended zero (SE0#), error conditions, and interconnect speed. (Inputs to SIE). VP 4, 5 VP, VM O 0 0 1 1 VM 0 1 0 1 RESULT SE0# Low Speed Full Speed Error
11, 10 6 9 14 7
D+, D SUSPND SPEED VCC GND
AI/O I I
Data+, Data. Differential data bus conforming to the Universal Serial Bus standard. Suspend. Enables a low power state while the USB bus is inactive. While the suspnd pin is active it will drive the RCV pin to a logic "0" state. Both D+ and D are tri-stated. Edge rate control. Logic "1" operates at edge rates for "full speed". Logic "0" operates edge rates for "low speed". 3.0V to 3.6V power supply Ground reference
2001 Jun 12
3
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