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Details, datasheet, quote on part number:PDUSBD12PWDH
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Datasheet text preview:
INTEGRATED CIRCUITS
PDIUSBD12 USB interface device with parallel bus
Product specification Supersedes data of 1998 Sep 24 1999 Jan 08
Philips Semiconductors
Philips Semiconductors
Product specification
USB interface device with parallel bus
PDIUSBD12
FEATURES
· Complies with the Universal Serial Bus specification Rev. 1.1 · High performance USB interface device with integrated SIE,
FIFO memory, transceiver and voltage regulator
DESCRIPTION
The PDIUSBD12 is a cost and feature-optimized USB device. It is normally used in microcontroller-based systems and communicates with the system microcontroller over the high speed general-purpose parallel interface. It also supports local DMA transfer. This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments. This results in the fastest way to develop the most cost-effective USB peripheral solution. The PDIUSBD12 fully conforms to the USB specification Rev. 1.1. It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations. The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPI, OnNOW, and USB power management requirements. The low operating power allows the implementation of bus-powered peripherals. In addition, it also incorporates features like SoftConnectTM, GoodLinkTM, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals.
· Compliant with most Device Class specifications · High-speed (2 Mbytes/s) parallel interface to any external
microcontroller/microprocessor
· Fully autonomous DMA operation · Integrated 320 bytes of multi-configuration FIFO memory · Double buffering scheme for main endpoint increases throughput
and eases real time data transfer
· 1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data
transfer rate achievable in Isochronous mode
· Bus-powered capability with very good EMI performance · Controllable LazyClock output during suspend · Software controllable connection to the USB bus (SoftConnectTM) · Good USB connection indicator that blinks with traffic
(GoodLinkTM)
· Programmable clock frequency output · Complies with the ACPI, OnNOW, and USB power management
requirements
· Internal power-on reset and low voltage reset circuit · Available in SO28 and TSSOP28 pin packages · Full industrial grade operation from 40 to +85°C · Higher than 8kV in-circuit ESD protection lowers cost of extra
components
· Full-scan design with high fault coverage (>99%) ensures high
quality
· Operation with dual voltages:
transfers
3.3 ± 0.3V or extended 5V supply range of 3.6 5.5V
· Multiple interrupt modes to facilitate both bulk and isochronous
ORDERING INFORMATION
PACKAGES 28-pin plastic SO 28-pin plastic TSSOP TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA PDIUSBD12 D PDIUSBD12 PW NORTH AMERICA PDIUSBD12 D PDUSBD12PW DH PKG. DWG. # SOT136-1 SOT361-1
1999 Jan 08
2
8532110 20620
Philips Semiconductors
Product specification
USB interface device with parallel bus
PDIUSBD12
BLOCK DIAGRAM
6 MHz
3.3V 1.5kW D+ SoftConnectTM
UPSTREAM PORT D+ D
PLL BIT CLOCK RECOVERY
INTEGRATED RAM
ANALOG TX/RX
PHILIPS SIE
MEMORY MANAGEMENT UNIT
VOLTAGE REGULATOR
PARALLEL AND DMA INTERFACE
SV00859
NOTE: * This is a conceptual block diagram and does not include each individual signal.
Analog Transceiver
The integrated transceiver interfaces directly to the USB cables through termination resistors.
Voltage Regulator
A 3.3V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 k pull-up resistor. Alternatively, the PDIUSBD12 provides SoftConnectTM technology with integrated 1.5 k pull-up resistor.
SoftConnectTM The connection to the USB is accomplished by bringing D+ (for high-speed USB device) high through a 1.5 k pull-up resistor. In the PDIUSBD12, the 1.5 k pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable.
The PDIUSBD12 will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through EOT_N pin. See the pin description for details. Sharing of VBUS sensing and EOT_N can be easily accomplished by using VBUS voltage as the pull up voltage for the normally open-drain output of the DMA controller pin. It should be noted that the tolerance of the internal resistors is higher (25%) than that specified by the USB specification (5%). However, the overall VSE voltage specification for the connection can still be met with good margin. The decision to make sure of this feature lies with the users. SoftConnectTM is a patent pending technology from Philips Semiconductors.
PLL
A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip. This allows for the use of low-cost 6 MHz crystal. EMI is also minimized due to the lower frequency crystal. No external components are needed for the operation of the PLL.
Bit Clock Recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification.
Philips Serial Interface Engine (PSIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation.
1999 Jan 08
3
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