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Details, datasheet, quote on part number:PLS100A
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| Part: | PLS100A |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) => Fuse-based FPGA/PAL |
| Description: | Programmable Logic Arrays |
| Company: | Philips Semiconductors |
| Datasheet: | Download PLS100A datasheet File size : 73 kB |
| Request For quote: | Find where to buy PLS100A
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Datasheet text preview:
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (16 × 48 × 8)
PLS100/PLS101
DESCRIPTION
The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations. Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don't Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output. The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems. Order codes are listed in the Ordering Information Table.
FEATURES
· Field-programmable (Ni-Cr link) · Input variables: 16 · Output functions: 8 · Product terms: 48 · I/O propagation delay: 50ns (max.) · Power dissipation: 600mW (typ.) · Input loading: 100µA (max.) · Chip Enable input · Output option:
PLS100: 3-State PLS101: Open-Collector
PIN CONFIGURATIONS
N Package
FE* 1 I7 2 I6 3 I5 4 I4 5 I3 6 I2 7 I1 8 I0 9 F7 10 F6 11 F5 12 F4 13 GND 14 28 VCC 27 I8 26 I9 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 CE 18 F0 17 F1 16 F2 15 F3
· Output disable function:
3-State: Hi-Z Open-Collector: High *
APPLICATIONS
· CRT display systems · Code conversion · Peripheral controllers · Function generators · Look-up and decision tables · Microprogramming · Address mapping · Character generators · Data security encoders · Fault detectors · Frequency synthesizers · 16-bit to 8-bit bus interface · Random logic replacement
Fuse Enable Pin: It is recommended that this pin be left open or connected to ground during normal operation.
N = Plastic DIP (600mil-wide)
A Package
I5 4 I4 I3 I2 I1 I0 5 6 7 8 9 I6 3 I7 FE VCC I8 I9 2 1 28 27 26 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 CE 12 13 14 15 16 17 18
F7 10 F6 11
F5 F4 GND F3 F2 F1 F0 A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION 28-Pin Plastic Dual In-Line 600mil-wide 28-Pin Plastic Leaded Chip Carrier 3-STATE PLS100N PLS100A OPEN COLLECTOR PLS101N PLS101A DRAWING NUMBER 0413D 0401F
October 22, 1993
49
8530308 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (16 × 48 × 8)
PLS100/PLS101
LOGIC DIAGRAM
(LOGIC TERMSP)
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15
9 8 7 6 5 4 3 2 27 26 25 24 23 22 21 20
S0 X0 X1 X2 X3 X4 X5 X6 X7 47 40 39 32 31 24 23 1615 87 0 S1 S2 S3 S4 S5 S6 S7
18 17 16 15 13 12 11 10 19
F0 F1 F2 F3 F4 F5 F6 F7 CE
NOTES: 1. All AND gate inputs with a blown link float to a logic "1". 2. All OR gate inputs with a blown fuse float to logic "0". 3. Programmable connection.
October 22, 1993
50
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays (16 × 48 × 8)
PLS100/PLS101
FUNCTIONAL DIAGRAM
I0
TYPICAL CONNECTION
I1
I15
TYPICAL CONNECTION
S0 F0 S6 F6 S7 F7
P0
P1
P 47
CE
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VCC VIN VO IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input current Output current Operating temperature range Storage temperature range RATINGS +7.0 +5.5 +5.5 ±30 +100 0 to +75 65 to +150 UNIT VDC VDC VDC mA mA °C °C
NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied.
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150°C 75°C 75°C
The PLS100 device is also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook.
October 22, 1993
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