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Details, datasheet, quote on part number:SA5090N
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| Part: | SA5090N |
| Category: | Timing Circuits => Timers => Timers, oscillators and counters |
| Description: | NE/SA5090; Addressable Relay Driver;; Package: SOT38-4 (DIP16) |
| Company: | Philips Semiconductors |
| Datasheet: | Download SA5090N datasheet File size : 102 kB |
| Request For quote: | Find where to buy SA5090N
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Datasheet text preview:
INTEGRATED CIRCUITS
NE/SA5090 Addressable relay driver
Product data Supersedes data of 1994 Aug 31 File under Integrated Circuits; IC11 Data Handbook 2001 Aug 03
Philips Semiconductors
Philips Semiconductors
Product data
Addressable relay driver
NE/SA5090
DESCRIPTION
The NE/SA5090 addressable relay driver is a high-current latched driver, similar in function to the 9934 address decoder. The device has 8 open-collector Darlington power outputs, each capable of 150 mA load current. The outputs are turned on or off by respectively loading a logic "1" or logic "0" into the device data input. The required output is defined by a 3-bit address. The device must be enabled by a CE input line which also serves the function of further address decoding. A common clear input, CLR, turns all outputs off when a logic "0" is applied. The device is packaged in a 16-pin plastic DIP or SO package.
PIN CONFIGURATION
D1, N Packages
A0 1 A1 2 A2 3 Q0 4 Q1 5 16 15 14 13 12 11 10 9 V CC CLR CE D Q7 Q6 Q5 Q4
Q2 6 Q3 7
FEATURES
GND 8
· 8 high-current outputs · Low-loading bus-compatible inputs · Power-on clear ensures safe operation · Will operate in addressable or demultiplex mode · Allows random (addressed) data entry · Easily expandable · Pin-compatible with 9334 (Philips or Fairchild)
TOP VIEW
NOTE: 1. SOL - Released in Large SO package only.
SL00234
Figure 1. Pin Configuration
APPLICATIONS
· Relay driver · Indicator lamp driver · Triac trigger · LED display digit driver · Stepper motor driver
BLOCK DIAGRAM
CLR LATCH LATCH LATCH LATCH A1 1OF8 DECODER CONTROL GATE LATCH LATCH LATCH LATCH Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CE A0
A2 D
INPUT STAGE V CC
OUTPUT STAGE
SL00235
Figure 2. Block Diagram
2001 Aug 03
2
853-0892 26833
Philips Semiconductors
Product data
Addressable relay driver
NE/SA5090
PIN DESIGNATION
PIN NO. 1-3 4-7, 9-12 13 SYMBOL A0-A2 Q0-Q7 D NAME AND FUNCTION A 3-bit binary address on these pins defines which of the 8 output latches is to receive the data. The 8 device outputs. The data input. When the chip is enabled, this data bit is transferred to the defined output such that: "1" turns output switch "ON" "0" turns output switch "OFF" 14 15 CE CLR The chip enable. When this input is low, the output latches will accept data. When CE goes high, all outputs will retain their existing state, regardless of address of data input condition. The clear input. When CLR goes low all output switches are turned "OFF". The high data input will override the clear function on the addressed latch.
ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic Small Outline Large (SOL) Package 16-Pin Plastic Dual In-Line Package (DIP) 16-Pin Plastic Small Outline Large (SOL) Package 16-Pin Plastic Dual In-Line Package (DIP) TEMPERATURE RANGE 0 °C to +70 °C 0 °C to +70 °C 40 °C to +85 °C 40 °C to +85 °C ORDER CODE NE5090D NE5090N SA5090D SA5090N DWG # SOT1621 SOT384 SOT1621 SOT384
TRUTH TABLE
INPUTS CLR L L L L L L L H H H H H H H CE H L L L L L L H L L L L L L D X L H L H L H X L H L H L H A0 X L L H H H H X L L H H H H A1 X L L L L H H X L L L L H H A2 X L L L L H H X L L L L H H Q0 H H L H H H H QN-1 H L QN1 QN 1 QN 1 QN1 QN1 QN1 H L QN 1 QN 1 H L Addressable Latch Latch Q1 H H H H L H H Q2 H H H H H H H OUTPUTS Q3 H H H H H H H Q4 H H H H H H H Q5 H H H H H H H Q6 H H H H H H H Q7 H H H H H H L Memory Demultiplex Clear MODE
NOTES: X=Don't care condition QN-1=Previous output state L=Low voltage level/"ON" output state H=High voltage level/"OFF" output state
2001 Aug 03
3
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