Details, datasheet, quote on part number: SSTU32865ET/G
PartSSTU32865ET/G
CategoryLogic => Buffers/Drivers
Description1.8 V 28-bit 1:2 Registered Buffer With Parity For DDR2 Rdimm Applications<<<>>>the SSTU32865 is a 1.8 V 28-bit 1:2 Register Specifically Designed For Use on Two Rank BY Four (2Rx4) And Similar High-density DDR2 Memory Modules. It is Similar in Function to The Jedec-standard 14-bit DDR2 Register, But Integrates The Functionality of The Normally Required Two Registers in a Single Package, Thereby Freeing up Board Real-estate And Facilitating Routing to Accommodate High-density Dimm Designs. <<<>>><<<>>>The SSTU32865 Also Integrates a Parity Function, Which Accepts a Parity Bit From The Memory Controller, Compares it With The Data Received on The D-inputs And Indicates Whether a Parity Error Has Occurred on Its Open-drain Ptyerr Pin (active-LOW). <<<>>><<<>>>The SSTU32865 is Packaged in a 160-ball, 12 X 18 Grid, 0.65 MM Ball Pitch Tfbga Package, Which While Requiring a Minimum 9x 13 MM of Board Space Allows For Adequate Signal Routing And Escape Using Conventional Card Technology. <<<>>><<<>>> <<<>>> Features 28-bit Data Register Supporting DDR2 <<<>>>Fully Compliant to Jedec Standard JESD82-9 <<<>>>Supports 2 Rank BY 4 Dimm Density BY Integrating Equivalent Functionality of Two Jedec-standard DDR2 Registers (i.e. 2x SSTU32864 or 2x SSTU32866) <<<>>>Parity Checking Function Across 22 Input Data Bits <<<>>>Parity Out Signal <<<>>>Single 1.8 V Supply Operation <<<>>>Available in 160-ball 9x 13 Mm, 0.65 MM Ball Pitch Tfbga Package <<<>>><<<>>> <<<>>> Applications High-density (e.g. 2 Rank BY 4) DDR2 Registered Dimms <<<>>>DDR2 Registered Dimms Desiring Parity Checking Functionality
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload SSTU32865ET/G datasheet
Cross ref.Similar parts: 74SSTUB32864A, 74SSTUB32865, 74SSTUB32865A, 74SSTUB32866A, 74SSTUB32868, SN74SSTU32864, SN74SSTU32864C, SN74SSTUB32864, SN74SSTUB32866
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PackagesSOT802-1
  

 

Features, Applications
28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications

The 28-bit 1:2 register specifically designed for use on two rank by four (2Rx4) and similar high-density DDR2 memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density DIMM designs. The SSTU32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active-LOW). The SSTU32865 is packaged 18 grid, 0.65 mm ball pitch TFBGA package, which--while requiring a minimum mm of board space--allows for adequate signal routing and escape using conventional card technology.

s 28-bit data register supporting DDR2 s Fully compliant to JEDEC standard JESD82-9 s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (i.e. SSTU32866) s Parity checking function across 22 input data bits s Parity out signal s Single 1.8 V supply operation s Available 13 mm, 0.65 mm ball pitch TFBGA package

s High-density (e.g. 2 rank 4) DDR2 registered DIMMs s DDR2 registered DIMMs desiring parity checking functionality

Table 1: Ordering information Package Name SSTU32865ET TFBGA160 Description plastic thin ball grid array package; 160 balls; body mm plastic thin ball grid array package; 160 balls; body mm Solder process Version Pb-free (SnAgCu solder ball SOT802-1 compound) SnPb solder ball compound SOT802-1 Type number

Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Table 2: Ball mapping 18 grid; top view. An empty cell indicates no ball is populated at that grid point. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH. VREF D18 CK RESET DODT1 DCKE0 VREF DODT0 DCKE1 MCL PTYERR MCH NC MCH Q4B Q4A VDDL GND VDDL GND VDDL GND VDDL GND VDDL VDDR GND NC VDDL NC VDDR GND 3 PARIN Q18A Q17B


 

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