Details, datasheet, quote on part number: SSTU32866EC
PartSSTU32866EC
CategoryLogic => Buffers/Drivers
Description1.8 V 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer With Parity For DDR2 Rdimm Applications <<<>>>The SSTU32866 is a 1.8 V Configurable Register Specifically Designed For Use on DDR2 Memory Modules Requiring a Parity Checking Function. It is Defined in Accordance With The Jedec JESD82-7 Standard For The SSTU32864 Registered Buffer, While Adding The Parity Checking Function in a Compatible Pinout. The Jedec Standard For SSTU32866 is Pending Publication. The Register is Configurable (using Configuration Pins C0 And C1) to Two Topologies: 25-bit 1:1 or 14-bit 1:2, And in The Latter Configuration CAN be Designated as Register a or Register B on The Dimm. <<<>>><<<>>>The SSTU32866 Accepts a Parity Bit From The Memory Controller on Its Parity Bit (PAR_IN) Input, Compares it With The Data Received on The Dimm-independent D-inputs And Indicates Whether a Parity Error Has Occurred on Its Open-drain Qerr Pin (active-LOW). The Convention is Even Parity, I.e., Valid Parity is Defined as an Even Number of Ones Across The Dimm-independent Data Inputs Combined With The Parity Input Bit. <<<>>><<<>>>The SSTU32866 is Packaged in a 96-ball, 6 X 16 Grid, 0.8 MM Ball Pitch Lfbga Package (13.5 MM BY 5.5 Mm). <<<>>><<<>>> <<<>>> Features Configurable Register Supporting DDR2 Registered Dimm Applications <<<>>>Configurable to 25-bit 1:1 Mode or 14-bit 1:2 Mode <<<>>>Controlled Output Impedance Drivers Enable Optimal Signal Integrity And Speed <<<>>>Exceeds JESD82-7 Speed Performance (1.8 NS Max. Single-bit Switching Propagation Delay; 2.0 NS Max. Mass-switching) <<<>>>Supports up to 450 MHZ Clock Frequency of Operation <<<>>>Optimized Pinout For High-density DDR2 Module Design <<<>>>Chip-selects Minimize Power Consumption BY Gating Data Outputs From Changing State <<<>>>Supports SSTL_18 Data Inputs <<<>>>Checks Parity on The Dimm-independent Data Inputs <<<>>>Partial Parity Output And Input Allows Cascading of Two SSTU32866s For Correct Parity Error Processing <<<>>>Differential Clock (CK And CK) Inputs <<<>>>Supports Lvcmos Switching Levels on The Control And Reset Inputs <<<>>>Single 1.8 V Supply Operation <<<>>>Available in 96-ball, 13.5 X 5.5 Mm, 0.8 MM Ball Pitch Lfbga Package <<<>>><<<>>> <<<>>> Applications DDR2 Registered Dimms Desiring Parity Checking Functionality
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload SSTU32866EC datasheet
Cross ref.Similar parts: 74SSTUB32864A, 74SSTUB32865, 74SSTUB32865A, 74SSTUB32866A, 74SSTUB32868, 74SSTUB32868A, SN74SSTU32864, SN74SSTU32864C, SN74SSTUB32866, SN74SSTEB32866
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PackagesSOT536-1 (LFBGA96)
  

 

Features, Applications
14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications

The 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 14-bit 1:2, and in the latter configuration can be designated as Register A or Register B on the DIMM. The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTU32866 is packaged 16 grid, 0.8 mm ball pitch LFBGA package by 5.5 mm).

Configurable register supporting DDR2 Registered DIMM applications Configurable 25-bit 1:1 mode 14-bit 1:2 mode Controlled output impedance drivers enable optimal signal integrity and speed Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) Supports to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Checks parity on the DIMM-independent data inputs Partial parity output and input allows cascading of two SSTU32866s for correct parity error processing Differential clock (CK and CK) inputs Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation Available 5.5 mm, 0.8 mm ball pitch LFBGA package

s DDR2 registered DIMMs desiring parity checking functionality

Table 1: Ordering information Tamb to +70 C. Type number Package Name SSTU32866EC LFBGA96 Description plastic low profile fine-pitch ball grid array package; 96 balls; body mm plastic low profile fine-pitch ball grid array package; 96 balls; body mm Solder process Version Pb-free (SnAgCu solder ball SOT536-1 compound) SnPb solder ball compound SOT536-1

Table 2: Ball mapping, 1:1 register 16 grid; top view. DNU denotes `Do Not Use'. NC denotes a no-connect (ball present but not connected to the die). DCKE D2 D3 DODT D5 D6 PAR_IN D14 2 PPO D15 D16 QERR D17 D18 RESET DCS CSR D25 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD 5 QCKE Q2 Q3 QODT Q6 C1 QCS Q14 6 DNU Q15 Q16 DNU Q18 C0 DNU Q24 Q25

Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Table 3: Ball mapping, 1:2 Register 16 grid; top view. DNU denotes `Do Not Use'. NC denotes a no-connect (ball present but not connected to the die). DCKE D2 D3 DODT D5 D6 PAR_IN D14 2 PPO DNU QERR NC RESET DCS CSR DNU 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD 5 QCKEA Q2A Q3A QODTA Q6A C1 QCSA Q14A 6 QCKEB Q2B Q3B QODTB Q6B C0 QCSB Q13B Q14B

Table 4: Ball mapping, 1:2 Register 16 grid; top view. DNU denotes `Do Not Use'. NC denotes a no-connect (ball present but not connected to the die). D5 D6 PAR_IN D9 D10 DODT D12 D13 DCKE 2 PPO DNU QERR DNU RESET DCS CSR DNU 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD Q6A C1 QCSA Q9A Q10A QODTA Q12A Q13A QCKEA Q6B C0 QCSB Q9B Q10B QODTB Q12B Q13B QCKEB


 

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