|Category||Logic => Memory Interface|
|Description||SSTV16857; 14-bit SSTL_2 Registered Driver With Differential Clock Inputs;; Package: SOT362-1 (TSSOP48), SOT480-1 (TSSOP48), SOT702-1 (VFBGA56)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download SSTV16857 datasheet
|Cross ref.||Similar parts: 74SSTV16857, CY2SSTV16857ZC, HD74SSTV16857, PI74SSTV16857DA, SN74SSTV16857, SN74SSTV16857DGGR, SSTV16857DGG, SSTV16857DGV|
14-bit SSTL_2 registered driver with differential clock inputs
Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) Optimized for DDR (Double Data Rate) SDRAM applications Inputs compatible with JESD89 SSTL_2 specifications. Flow-through architecture optimizes PCB layout ESD classification testing is done to JEDEC Standard JESD22. Latch-up testing is done to JEDEC Standard JESD78, which Same form, fit, and function as SSTL16877 Full DDR 200/266 solution 2.5 V when used with PCKV857 See SSTV16856 for driver/buffer version with mode select. Available TSSOP-48, TVSOP-48 and 56 ball VFBGA packagesDESCRIPTION
The 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. exceeds 100 mA. Protection exceeds V to HBM per method A114.
Q1 Q2 GND VDDQ Q4 Q5 GND VDDQ D2 46 GND 45 VCC D7 39 CLK 38 CLK+ 37 VCC 36 GND 35 VREF 34 RESET D12 28 VCC 27 GND 25 D14
GND 0 V; Tamb 25°C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS = 30 pF; VDDQ 2.5 V VCC 2.5 V TYPICAL 2.4 2.9 UNIT ns pF
PACKAGES 48-Pin Plastic TSSOP 48-Pin Plastic TSSOP (TVSOP) 56-Ball Plastic VFBGA TEMPERATURE RANGE +70 °C ORDER CODE SSTV16857DGV SSTV16857EV DWG NUMBER SOT480-1 SOT702-1Ground (0 V) Positive supply voltage Output supply voltage
H = High voltage level L = High voltage level = High-to-Low transition = Low-to-High transition X = Don't care
|Related products with the same datasheet|
|Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)|
|SSTV16857DGG SSTV16857; 14-bit SSTL_2 Registered Driver With Differential Clock Inputs;; Package: SOT362-1 (TSSOP48), SOT480-1 (TSSOP48), SOT702-1 (VFBGA56)|
|SSTV16859 SSTV16859; 2.5 V 13-bit to 26-bit SSTL_2 Registered Buffer For Stacked DDR DIMM;; Package: SOT536-1 (LFBGA96), SOT684-1 (HVQFN56)|
|SSTVF16857 DDR PC1600-PC3200 14-bit SSTL_2 Registered Driver With Differential Clock Inputs<<<>>>the SSTVF16857 is a 14-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V. VDDQ|
|SSTVF16859 13-bit 1:2 SSTL_2 Registered Buffer For DDR <<<>>>The SSTVF16859 is a 13-bit to 26-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V For PC1600 PC2700|
|SSTVN16859 13-bit 1:2 SSTL_2 Registered Buffer For Ddr<<<>>>the SSTVN16859 is a 13-bit to 26-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V For PC1600 PC2700|
|STM1/4/16 Sdh/sonet Data And Clock Recovery Unit|
|SZA1000 Qic Digital Equalizer|
|SZA1010 SZA1010; Digital Servo Driver 3 (DSD-3)|
|SZA1015 SZA1015; Brushless Motor Controller (BMC12)|
|SZF2002 Low Voltage 8-bit Microcontroller With 6-kbyte Embedded RAM|
|T2322B T2322B; Triacs Logic Level|
|TBA120U Sound I.F. Amplifier/demodulator For TV|
|TCA280B General-purpose Triggering Circuit|
|TDA1001B Interference And Noise Suppression Circuit For FM Receivers|
|TDA10045H TDA10045H; Dvb-t Channel Receiver|
|TDA10085HT TDA10085HT; Single Chip Dvb-s/dss Channel Receiver|
|TDA1010A TDA1010A; 6 W Audio Power Amplifier in Car Applications 10 W Audio Power Amplifier in Mains-fed Applications|
74LV240 : Bus Oriented Circuits 74LV240; Octal Buffer/line Driver; Inverting (3-State)
74LVC02APW : 74LVC02A; Quad 2-input NOR GATE;; Package: SOT108-1 (SO14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
7AHCT244PWDH : Octal Buffer/line Driver; 3-state
BFQ17 : BFQ17; NPN 1 GHZ Wideband Transistor;; Package: SOT89 (MPT3, UPAK)
HEF40106BPB : HEF40106B; Hex Inverting Schmitt Trigger;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
HEF4541BPN : HEF4541B MSI; Programmable Timer;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
PZU3.6B2L : Single Zener Diodes General-purpose Zener diodes in SOD882 leadless ultra small Surface-Mounted Device (SMD) plastic package.
LXZ1-PB01 : High Power LEDs - Single Color Blue Philips Lumileds LUXEON& 174; Z Color & White LEDs are extraordinarily small, un-domed, power LEDs in colors from 440nm to 670nm and 4000K white. With never before possible lumen density, flexibility, and freedom of design in color and white LEDs, the LUXEON& 174; Z will transform luminaire and ligh
74LVT162373 : 74LVT162373; 3.3 V LVT 16-bit Transparent D-type Latch With 30 Ohm Termination Resistors (3-State);; Package: SOT362-1 (TSSOP48), SOT370-1 (SSOP48).
74LVTH2244 : CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage. Low Voltage Octal Buffer/line Driver With 3-STATE Outputs.
74V1G07S : Single Buffer Open Drain. HIGH SPEED: tPD 6.1 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC 1 µA (MAX.) 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUT OPERATING VOLTAGE RANGE: VCC (OPR) to 5.5V IMPROVED LATCH-UP IMMUNITY ORDER CODE: 74V1G07S 74V1G07C Power down protection is provided on input and to 7V can be accepted on input with.
CD54HC154 : CMOS/BiCMOS->HC/HCT Family. High Speed CMOS Logic 4-to-16 Line Decoder/demultiplexer.
HCF4519BEY : 4 Bit And/or Selector. VERY LOW QUIESCENT CURRENT HIGH NOISE IMMUNITY SUPPLY VOLTAGE RANGE TO 18V SINGLE SUPPLY VOLTAGE - POSITIVE OR NEGATIVE LOGIC SWING INDEPENDENT OF FANOUT M1 C1 (Micro Package) (Plastic Chip Carrier) ORDER CODES BM1 HCF4519 BEY HCF4519 BC1 The HCC4519B and HCF4519B are monolithic integrated circuits, available in 16-lead dual-in-line plastic or ceramic.
HD74HC597 : 8-bit Latch/shift Register. Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.
IN74AC244DW : Octal Buffer/line Driver Ninv (3-State) 20. The IN74AC244 is identical in pinout to the LS/ALS244, HC/HCT244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems.
M54HC699B1R : Hc697/699 U/d 4 Bit Binary Counter/register 3-state Hc696/698 U/d Decade Counter/register 3-state.
MC10E167 : Bipolar->ECL 10 Family. 6-bit 2:1 Mux Register. The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW. The 100 Series contains temperature.
SN5425N : Dual 4-input NOR GATEs With Strobe.
SN74AC241DBLE : Non-Inverting Buffers and Drivers. ti SN74AC241, Octal Buffers/drivers With 3-State Outputs.
TPD3E001 : Low-Capacitance 2-Channel +/-15-kV ESD-Protection Array for High-Speed Data Interfaces The TPD3E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The TPD2E001 protects against ESD pulses.
MAX9360 : LVTTL/TTL/CMOS-to-Differential LVECL/ECL Translators The MAX9360/MAX9361 are low-skew, single LVTTL/TTL/CMOS-to-differential LVECL/ECL translators designed for high-speed signal and clock driver applications. For interfacing to LVTTL/TTL/CMOS input signals, these devices operate over a 3.0V to 5.5V supply range, allowing high-performance clock or data.
M74LS13P : LS SERIES, DUAL 4-INPUT NAND GATE, PDIP14. s: Gate Type: NAND ; Supply Voltage: 5V ; Logic Family: TTL ; Inputs: 4 ; Propagation Delay: 27 ns ; Operating Temperature: -20 to 75 C (-4 to 167 F) ; Pin Count: 14 ; IC Package Type: DIP, Other, PLASTIC, DIP-14.
XA3SD3400A-FGG676I : FPGA, PBGA676. s: Device Type: FPGA ; Package Type: Other, LEAD FREE, FBBGA-676 ; Pins: 676.
74F538SJX : F/FAST SERIES, OTHER DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO20. s: Function: Decoder ; Supply Voltage: 5V ; Package Type: SOP, 5.30 MM, EIAJ TYPE2, SOP-20 ; Logic Family: TTL ; Number of Pins: 20 ; Propagation Delay: 17 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).