Details, datasheet, quote on part number: SSTV16857
CategoryLogic => Memory Interface
DescriptionSSTV16857; 14-bit SSTL_2 Registered Driver With Differential Clock Inputs;; Package: SOT362-1 (TSSOP48), SOT480-1 (TSSOP48), SOT702-1 (VFBGA56)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload SSTV16857 datasheet
Cross ref.Similar parts: 74SSTV16857, CY2SSTV16857ZC, HD74SSTV16857, PI74SSTV16857DA, SN74SSTV16857, SN74SSTV16857DGGR, SSTV16857DGG, SSTV16857DGV
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Features, Applications

14-bit SSTL_2 registered driver with differential clock inputs

Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) Optimized for DDR (Double Data Rate) SDRAM applications Inputs compatible with JESD89 SSTL_2 specifications. Flow-through architecture optimizes PCB layout ESD classification testing is done to JEDEC Standard JESD22. Latch-up testing is done to JEDEC Standard JESD78, which Same form, fit, and function as SSTL16877 Full DDR 200/266 solution 2.5 V when used with PCKV857 See SSTV16856 for driver/buffer version with mode select. Available TSSOP-48, TVSOP-48 and 56 ball VFBGA packages


The 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. exceeds 100 mA. Protection exceeds V to HBM per method A114.

Q1 Q2 GND VDDQ Q4 Q5 GND VDDQ D2 46 GND 45 VCC D7 39 CLK 38 CLK+ 37 VCC 36 GND 35 VREF 34 RESET D12 28 VCC 27 GND 25 D14

GND 0 V; Tamb 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS = 30 pF; VDDQ 2.5 V VCC 2.5 V TYPICAL 2.4 2.9 UNIT ns pF


Ground (0 V) Positive supply voltage Output supply voltage

H = High voltage level L = High voltage level = High-to-Low transition = Low-to-High transition X = Don't care


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