|Category||Timing Circuits => Clock Circuits|
|Description||SSTV16859; 2.5 V 13-bit to 26-bit SSTL_2 Registered Buffer For Stacked DDR DIMM;; Package: SOT536-1 (LFBGA96), SOT684-1 (HVQFN56)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download SSTV16859 datasheet
|Cross ref.||Similar parts: 74SSTV16859, PI74SSTV16859, HD74SSTV16859, PI74SSTV16859A, SN74SSTV16859, SN74SSTV16859DGGR, SSTV16859BS, SSTV16859DGG|
Product data 2000 Dec 01 File under Integrated Circuits ICL03 2002 Feb 19
Stub-series terminated logic for 2.5 V VDD (SSTL_2) Optimized for stacked DDR (Double Data Rate) SDRAMapplications
DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going high, and CK going low. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven low. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the outputs will remain low. Available in 64-pin plastic thin shrink small outline package.
Supports SSTL_2 signal inputs as per JESD 89 Flow-through architecture optimizes PCB layout ESD classification testing is done to JEDEC Standard JESD22.Latch-up testing is done to JEDEC Standard JESD78, which
Supports efficient low power standby operation Full DDR 200/266 solution for stacked DIMMs 2.5 V when usedDESCRIPTION
The 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as
GND 0 V; Tamb v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS = 30 pF; VDD 2.5 V VCC 2.5 V TYPICAL 2.4 2.7 UNIT ns pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD fi + (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 × fo) = sum of the outputs.
PACKAGES 64-Pin Plastic TSSOP 96-Ball Plastic LFBGA 56-Terminal Plastic HVQFN TEMPERATURE RANGE +70 °C ORDER CODE SSTV16859EC SSTV16859BS DWG NUMBER SOT536-1 SOT684-1
Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK Input reference voltage Positive and negative master clock input Asynchronous reset input: resets registers and disables data and clock differential input receivers
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