Details, datasheet, quote on part number: SSTVF16857DGG
PartSSTVF16857DGG
CategoryLogic => Buffers/Drivers
DescriptionDDR PC1600-PC3200 14-bit SSTL_2 Registered Driver With Differential Clock Inputs<<<>>>the SSTVF16857 is a 14-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V. VDDQ Must Not Exceed VCC . Inputs Are SSTL_2 Type With Vref Normally at 0.5*VDDQ . The Outputs Support Class i Which CAN be Used For Standard Stub-series Applications or Capacitive Loads. Master Reset (RESET) Asynchronously Resets All Registers to Zero.
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload SSTVF16857DGG datasheet
Cross ref.Similar parts: SN74SSTVF16857GR
Quote
Find where to buy
 
PackagesSOT362-1 (TSSOP48)
  

 

Features, Applications

SSTVF16857 DDR 14-bit SSTL_2 registered driver with differential clock inputs
DDR 14-bit SSTL_2 registered driver with differential clock inputs
FEATURES

Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) Optimized for PC 2700 DDR (Double Data Rate) SDRAM Suitable for PC1600/PC2100 DDR SDRAM applications Suitable for PC3200 applications when used at VDD 2.6 V Inputs compatible with JESD8-9 SSTL_2 specifications. Flow-through architecture optimizes PCB layout ESD classification testing is done to JEDEC Standard JESD22. Latch-up testing is done to JEDEC Standard JESD78, which Full DDR300/333/400 solution @ 2.5V when used with PCKV857 Available TSSOP-48, TVSOP-48 and 56 ball VFBGA packages Superior VREF noise rejection

DESCRIPTION

The 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of 333 MT/s (mega-transfers per second). The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTVF16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. exceeds 100 mA. Protection exceeds V to HBM per method A114. applications

GND 0 V; Tamb 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS = 30 pF; VDDQ 2.5 V VCC 2.5 V TYPICAL 1.9 2.9 UNIT ns pF

DDR 14-bit SSTL_2 registered driver with differential clock inputs

PACKAGES 48-Pin Plastic TSSOP Type I 48-Pin Plastic TSSOP (TVSOP) 56-Ball Plastic VFBGA TEMPERATURE RANGE +70 C ORDER CODE SSTVF16857DGV SSTVF16857EV DWG NUMBER SOT480-1 SOT702-1

SSTL_2 data outputs SSTL_2 input reference level Ground (0 V) Positive supply voltage Output supply voltage Differential clock inputs

H = High voltage level L = High voltage level = High-to-Low transition = Low-to-High transition X = Don't care


 

Related products with the same datasheet
SSTVF16857DGV
SSTVF16857EV
Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
SSTVF16857DGV DDR PC1600-PC3200 14-bit SSTL_2 Registered Driver With Differential Clock Inputs<<<>>>the SSTVF16857 is a 14-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V. VDDQ
SSTVF16859 13-bit 1:2 SSTL_2 Registered Buffer For DDR <<<>>>The SSTVF16859 is a 13-bit to 26-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V For PC1600 PC2700
SSTVN16859 13-bit 1:2 SSTL_2 Registered Buffer For Ddr<<<>>>the SSTVN16859 is a 13-bit to 26-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3 V And 2.7 V For PC1600 PC2700
STM1/4/16 Sdh/sonet Data And Clock Recovery Unit
SZA1000 Qic Digital Equalizer
SZA1000H
SZA1010 SZA1010; Digital Servo Driver 3 (DSD-3)
SZA1015 SZA1015; Brushless Motor Controller (BMC12)
SZF2002 Low Voltage 8-bit Microcontroller With 6-kbyte Embedded RAM
SZF2002HL
T2322B T2322B; Triacs Logic Level
TBA120U Sound I.F. Amplifier/demodulator For TV
TCA280B General-purpose Triggering Circuit
TDA1001B Interference And Noise Suppression Circuit For FM Receivers
TDA10021HT
TDA10045H TDA10045H; Dvb-t Channel Receiver
TDA10085
TDA10085HT TDA10085HT; Single Chip Dvb-s/dss Channel Receiver
TDA1010A TDA1010A; 6 W Audio Power Amplifier in Car Applications 10 W Audio Power Amplifier in Mains-fed Applications
TDA1011 2 to 6 W Audio Power Amplifier
TDA1011A 2 to 6w Audio Power Amplifier With Preamplifier
 
0-C     D-L     M-R     S-Z