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Details, datasheet, quote on part number:VC162373ADGG
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| Part: | VC162373ADGG |
| Category: | Interface and Interconnect => Terminations |
| Description: | 16-bit D-type Transparent Latch With 30 Ohm Series Termination Resistors; 5 V Input/output Tolerant; 3-state |
| Company: | Philips Semiconductors |
| Datasheet: | Download VC162373ADGG datasheet File size : 90 kB |
| Request For quote: | Find where to buy VC162373ADGG
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74LVC162373A; 74LVCH162373A 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state
Product specification File under Integrated Circuits, IC24 1999 Aug 05
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 30 series 74LVC162373A; termination resistors; 5 V input/output tolerant; 3-state 74LVCH162373A
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V · 5 V tolerant input/output for interfacing with 5 V logic · Wide supply voltage range of 1.2 to 3.6 V · Complies with JEDEC standard no. 8-1A · CMOS low power consumption · MULTIBYTETM flow-through standard pin-out architecture · Low inductance multiple power and ground pins for minimum noise and ground bounce · Direct interface with TTL levels · All data inputs have bus hold (74LVCH162373A only) · High impedance when VCC = 0 · Power off disables outputs, permitting live insertion. FUNCTION TABLE (per section of eight bits) See note 1. INPUTS OPERATION MODES OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. L L L L H H LE H H L L L L Dn L H l h l h INTERNAL LATCHES L H L H L H OUTPUTS Q0 to Q7 L H L H Z Z DESCRIPTION The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE) are provide for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. The 74LVC(H)162373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state off latches. The 74LVCH162373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. The 74LVC(H)162373A is designed with 30 series termination resistors in both HIGH and LOW output stages to reduce line noise.
1999 Aug 05
2
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH Dn to Qn LE to Qn CI CPD Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA 74LVC162373ADL 74LVC162373ADGG 74LVCH162373ADL 74LVCH162373ADGG PINNING PIN 1 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 24 25 1OE 1Q0 to 1Q7 GND VCC 2OE 2LE SYMBOL data inputs/outputs ground (0 V) DC supply voltage data inputs/outputs output enable input (active LOW) latch enable input (active HIGH) data inputs data inputs latch enable input (active HIGH) NORTH AMERICA VC162373A DL VC162373A DGG VCH162373A DL VCH162373A DGG TEMPERATURE RANGE -40 to +85 °C PINS 48 48 48 48 PACKAGE SSOP TSSOP SSOP TSSOP input capacitance power dissipation capacitance per latch VCC = 3.3 V; note 1 PARAMETER propagation delay CONDITIONS CL = 50 pF; VCC = 3.3 V
74LVC162373A; 74LVCH162373A
TYPICAL 3.2 3.5 5.0 26.0 ns ns pF pF
UNIT
MATERIAL plastic plastic plastic plastic
CODE SOT370-1 SOT362-1 SOT370-1 SOT362-1
DESCRIPTION output enable input (active LOW)
13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7
36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 48 1LE
1999 Aug 05
3
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