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Details, datasheet, quote on part number:VC16240ADGG
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Datasheet text preview:
INTEGRATED CIRCUITS
74LVC16240A 16-bit buffer/line driver; inverting (3-State)
Product specification Supersedes data of 1995 Dec 26 IC24 Data Handbook 1997 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit buffer/line driver; inverting (3-State)
74LVC16240A
FEATURES
· 5 volt tolerant inputs/outputs for interfacing with 5V logic · Wide supply voltage range of 1.2V to 3.6V · Complies with JEDEC standard no. 8-1A · CMOS low power consumption · MULTIBYTETM flow-through standard pin-out architecture · Low inductance multiple power and ground pins for minimum
noise and ground bounce
PIN CONFIGURATION
1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 1 2 3 4 5 6 7 8 9 48 2OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 2A0 40 2A1 39 GND 38 2A2 37 2A3 36 3A0 35 3A1 34 GND 33 3A2 32 3A3 31 VCC 30 4A0 29 4A1 28 GND 27 4A2 26 4A3 25 3OE
· Direct interface with TTL levels
DESCRIPTION
The 74LVC16240A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. The 74LVC16240A is a 16-bit inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LVC16240A is identical to the 74LVC16244A but has inverting outputs.
GND 10 2Y2 11 2Y3 12 3Y0 13 3Y1 14 GND 15 3Y2 16 3Y3 17 VCC 18 4Y0 19 4Y1 20 GND 21 4Y2 22 4Y3 23 4OE 24
SW00041
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 _C; tr = tf v 2.5 ns PARAMETER SYMBOL tPHL/tPLH CI CP D Propagation delay 1An to 1Yn; 2An to 2Yn Input capacitance Power dissipation capacitance per buffer VCC = 3.3V CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 2.7 5.0 25 UNIT ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC16240A DL 74LVC16240A DGG NORTH AMERICA VC16240A DL VC16240A DGG DWG NUMBER SOT370-1 SOT362-1
1997 Jul 29
2
853-2007 18218
Philips Semiconductors
Product specification
16-bit buffer/line driver; inverting (3-State)
74LVC16240A
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 5, 6 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 8, 9, 11, 12 13, 14, 16, 17 19, 20, 22, 23 24 25 30, 29, 27, 26 36, 35, 33, 32 41, 40, 38, 37 47, 46, 44, 43 48 SYMBOL 1OE 1Y0 to 1Y3 GND VCC 2Y0 to 2Y3 3Y0 to 3Y3 4Y0 to 4Y3 4OE 3OE 4A0 to 4A3 3A0 to 3A3 2A0 to 2A3 1A0 to 1A3 2OE NAME AND FUNCTION Output enable input (active LOW) Data outputs Ground (0V) Positive supply voltage Data outputs Data outputs Data outputs Output enable input (active LOW) Output enable input (active LOW) Data inputs Data inputs Data inputs Data inputs Output enable input (active LOW)
FUNCTION TABLE
INPUTS nOE L L H H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state nAn L H X OUTPUT nYn H L Z
LOGIC SYMBOL (IEEE/IEC)
1OE 2OE 3OE 4OE 1A0 1A1 1A2 1A3 2A0 2A1 1 48 25 24 47 46 44 43 41 1 40 38 37 36 35 33 32 30 29 27 26 1 4 1 3 2 EN1 EN2 EN3 EN4 1 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3
LOGIC SYMBOL
1A0 47 2 1Y0 3A0 36 13 3Y0
2A2 2A3 3A0 3A1
1A1
46
3
1Y1
3A1
35
14
3Y1
3A2 3A3
1A2
44
5
1Y2
3A2
33
16
3Y2
4A0 4A1
1A3
43
6
1Y3
3A3
32
17
3Y3
4A2 4A3
1OE
1
3OE
25
SW00059
2A0
41
8
2Y0
4A0
30
19
4Y0
2A1
40
9
2Y1
4A1
29
20
4Y1
2A2
38
11
2Y2
4A2
27
22
4Y2
2A3
37
12
2Y3
4A3
26
23
4Y3
2OE
48
4OE
24
SW00042
1997 Jul 29
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