|
Details, datasheet, quote on part number:XA-SCC
| |
Datasheet text preview:
INTEGRATED CIRCUITS
XA-SCC CMOS 16-bit communications microcontroller
Preliminary specification IC25 Data Handbook 1999 Feb 23
Philips Semiconductors
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
GENERAL DESCRIPTION
The XA-SCC device is a member of Philips' XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-SCC includes a complete onboard DRAM controller capable of supporting up to 32MegaBytes of DRAM. The XA-SCC device combines many powerful communications oriented peripherals on one chip. 4 Full Function SCC's, 8 DMA channels (2 per SCC), hardware autobaud up to 921.6Kbps, IDL TDM interface, two timers/counters, 1 watchdog timer, and multiple general purpose I/O ports. It is suited for many high performance embedded communications functions, including ISDN terminal adaptors and Asynchronous Muxes.
· Memory controller also generates 6 chip selects to support
SRAM, ROM, Flash, EPROM, peripheral chips, etc. without external glue.
· Supports off-chip addressing up to 32 MB (2 x 2**24 address
spaces) in Harvard architecture, or 16MB in unified memory configuration.
· A clock output reference "ClkOut" is added to simplify external bus
interfacing.
· High performance 8-channel DMA Controller offloads the CPU for
moving data to/from SCC's and memory.
· Two standard counter/timers with enhanced features (same as
XA-G3 T0, T1). Both timers have a toggle output capability.
SPECIFIC FEATURES OF THE XA-SCC
range, available in 100 pin LQFP package.
· 3.3V to 5.5V operation to 30MHz over the industrial temperature · 4 onboard SCC's for 2B+D plus Asynch port, or any combination
of 4 sync/async ports. Industry standard IDL and SCP interfaces for glueless connection to U-Chip or S/T chip. Sync data rates to 4Mbps. Asynch data rates to 921.6Kbps with/without autobaud.
· Watchdog timer. · Seven standard software interrupts, plus four High Priority
Software Interrupts, plus 7 levels of Hardware Event Interrupts.
· Active low reset output pin indicates all internal reset occurrences
(watchdog reset and the RESET instruction). A reset source register allows program determination of the cause of the most recent reset.
· Complete onboard DRAM controller supports 5 banks of up to
8MBytes each. Interfaces without glue chips to most industry standard DRAMs.
· 32 General Purpose I/O pins, each with 4 programmable output
configurations.
· Power saving operating modes: Idle and Power-Down. Wake-Up
from power-down via an external interrupt is supported.
ORDERING INFORMATION
ROMless Only PXASCCKFBE TEMPERATURE RANGE °C AND PACKAGE 40 to +85, 100-pin Low Profile Quad Flat Pkg. (LQFP) FREQ (MHz) 30 PACKAGE DRAWING NUMBER SOT407-1
NOTE: 1. K=30MHz, F = (40 to +85 °C), BE = LQFP
1999 Feb 23
2
Philips Semiconductors
Preliminary specification
CMOS 16-bit communications microcontroller
XA-SCC
PIN CONFIGURATION
P3.3_Timer1_BRG1_Sync1 56 P3.0_CS4_RAS4_RTClk1
P1.7_BRG2_Sync2
67 P3.7_Int1_TRClk1
P3.1_CS5_RAS5_RTS1
P3.2_Timer0_ResetOut
71 P1.3_TRClk2
70 P1.2_RTClk2
XTALOUT
Reset_In
XTALIN
VDD
VSS
BHE_CASH
P1.5_CTS2
P3.4_CTS1
P1.6_RTS2
P1.0_RxD2
P3.5_RxD1
BLE_CASL
P1.1_TxD2
P3.6_TxD1
P1.4_CD2
WAIT_Size16 52
75
74
73
72
69
68
66
65
64
63
62
61
60
59
58
57
55
54
53
VSS VDD CD1_Int2 Int0 P2.0_RxD3 P2.1_TxD3 P2.2_RTClk3 P2.3_ComClk_TRClk3 P2.4_CD3 P2.5_CTS3 P2.6_RTS3 P2.7_Sync3_BRG3 VSS VDD P0.0_Sync0_BRG0_SDS2 P0.1_RTS0_L1RQ P0.2_CTS0_L1GR P0.3_CD0_L1SY1 P0.4_TRClk0_SDS1 P0.5_RTClk0_L1Clk TxD0_L1TxD RxD0_L1RxD SCPClk P0.6_SCPTx
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
51 50 49 48 47 46 45 44 43 42 41 40
OE
WE CS0 CS1_RAS1 CS2_RAS2 CS3_RAS3 ClkOut VSS VDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 VDD VSS D2 D1
XA-SCC PLASTIC LOW PROFILE QUAD FLAT PACKAGE (LQFP) Top View
39 38 37 36 35 34 33 32 31 30 29 28 27 26
P0.7_SCPRx 100 10 12 13 14 15 16 17 18 19 20 21 22 23 24 A19 25 D0 11 A8 (A19_A20) 1 2 3 4 5 6 7 8 9
A7 (A21_A22)
A15 (A6_A22)
A11 (A2)
A16 (A7_A20_A21)
A17 (A8_A18_A19)
A9 (A0_A18)
A10 (A1)
A12 (A3)
A13 (A4)
A14 (A5)
A0
A1
A2
A3
A4
A5
A6
VSS
VDD
VSS
NOTE: Address lines output during various DRAM CAS cycles are shown in parentheses. See DRAM controller for details.
SU01120
1999 Feb 23
3
VDD
A18
|
|
