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Details, datasheet, quote on part number:PM5313-BI
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| Part: | PM5313-BI |
| Category: | Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => SONET/SDH Interface |
| Description: | Sonet/sdh Payload Extractor/aligner For 622 Mbit/s Interfaces |
| Company: | PMC-Sierra |
| Datasheet: | Download PM5313-BI datasheet File size : 130 kB |
| Request For quote: | Find where to buy PM5313-BI
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Datasheet text preview:
PMC-Sierra,Inc.
PM5313 SPECTRA-62 2
and Multiplexer Section transport-overhead. Also provides termination for Path overhead of twelve STS-1 (STM-0/AU3) paths, four STS-3/ 3c (STM-1/AU3/AU4) paths, or a single STS-12c (STM-4/AU4-4c) path. Maps twelve STS-1 (STM-0/AU3) payloads, four STS-3/3c (STM-1/AU3/ AU4) payloads, or a single STS-12c (STM-4/AU4-4c) payload to system timing references. This accommodates plesiochronous timing offsets between the references. Maps twelve DS3 bit-streams into an STS-12 (STM-4/AU3) frame. Configurable on an STS-1 basis to support a mix of traffic from the DS-3 and Telecom interfaces. Provides a Time-Slot Interchange (TSI) function on the Telecom Add and Drop buses for grooming twelve STS-1 (STM-0/AU3) paths or four STS-3/3c (STM-1/AU3/AU4) paths. Supports line loopback and diagnostic loopback. Supports OC-48 (STM-16) applications with byte interfaces for connection to an OC-48 front-end device. Supports diagnostic 223-1 pseudo-random bit-sequence (PRBS) generation and monitoring. Provides a standard JTAG test-port for boundary scan board-test purposes. Provides a generic 8-bit microprocessor bus-interface. Low-power 3.3V CMOS with TTL compatible inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible. Available in a 520-pin SBGA package. Supports industrial temperature-range (-40°C to 85°C) operation.
SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces
FEATURES
The SPECTRA-622 chip offers the following features: · Monolithic SONET/SDH Payload-Extractor/Aligner for use in STS-12 (STM-4/AU3 or STM-4/AU4) or STM-12c (STM-4/AU4-4c) interface applications that operate at serial interface speeds up to 622.08 Mbit/s. · Provides integrated clock recovery and clock synthesis to allow a direct interface to optical modules. · Complies with Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria. · Provides control circuitry required to comply with WAN clocking requirements for wander, holdover, and long term stability. · Provides termination for SONET Section and Line, and SDH Regenerator Section · ·
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TSLDCLK/TOWCLK TSLD/TSOW/TSUC TLDCLK/TOWCLK TLD/TLOW/TOH
TLRDI/TRCPFP RLAIS/TRCPCLK TLAIS/TRCPDAT
TTOH/TTOHREI TTOHFP TTOHCLK TTOHEN
BLOCK DIAGRAM
TPOH TPOHFP TPOHCLK TPOHEN TAD/TAFP/TACK TPOHRDY
SCPI[3:0] SCPO[1:0]
TCLK/PGMTCLK /TFP TC1J1V1/TFPO TFPI TDCK TXD+/TPL TD[7:0] TDP TDREF/ TDREF1 PECLV REFCLK+/RXD+/RRCLK+/SD C0, C1 PICLK PIN[7:0] FPIN OOF ATP[1:0] PREFEN PECLREF RCLK/PGMRCLK /RFP
Tx Ring Control Port Tx Transport O/H Controller
Transmit Path Processing Slice x12 DS3 Mapper Add Side Add Bus PRBS Generator/ Monitor
Serial Control Port Tx DS3 System I/F
TPAISCK TPAISFP TPAIS DS3TICLK [12:1] DS3TDAT [12:1] AC1J1V1[4:1]/ AFP[4:1] ACK APL[4:1] AD[31:0] ADP[4:1] DMODE[1:0] DCK DC1J1V1[4:1] DPL[4:1] DD[31:0] DDP[4:1] DFP DS3ROCLK [12:1] DS3RICLK DS3RDAT [12:1] DPAISCK DPAISFP DPAIS
Tx Line Interface
Tx Telecom Aligner
Tx Pointer Interpreter
Tx Path O/H Processor
Section Trace Buffer
Rx APS Synch Extractor & Bit Error Monitor
WAN Sync Controller
Rx Line Interface
Receive Path Processing Slice x12 Rx Telecom Aligner Drop Bus PRBS Generator/ Monitor
Path Trace Buffer
Rx Line O/H Processor
Rx Section O/H Processor
Clock & Data Recover y
Rx Ring Control Port
Rx Transport O/H Controller
Microprocessor Interface
JTAG Test Access Port
A[13:0] ALE CSB WRB, RWB RDB/E RSTB INTB MBEB
LOF, SALM RSLDCLK, ROWCLK RSLD, RSOW, RSUC RLDCLK, ROHCLK
LOS/RRCPFP
RPOH RPOHFP RPOHCLK RPOHEN RALM RTCEN RTCOH
LAIS/RRCPDAT LRDI/RRCPCLK
RLD, RLOW, ROH RTOH RTOHFP RTOHCLK
PMC-1981271 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT'S CUSTOMERS' INTERNAL USE
TDO TDI TCK TMS TRSTB
B3E RAD
D[7:0]
Rx DS3 System I/F
Rx Path O/H Processor
DS3 Mapper Drop Side
Rx Telecombus System Interface
Rx Timeslot Interchange
Tx Telecombus System Interface
Tx Line O/H Processor
Tx Section O/H Processor
Clock Synthesis
Tx Timeslot Interchange
2001 PMC-Sierra, Inc.
PM5313 SPECTRA-622 SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces
BACKPLANE/DEVICE MODES
· 77.76 MHz Telecom Byte · 19.44 MHz Telecom Byte x 4 · Datacom DS-3 x 12
APPLICATIONS
Use the SPECTRA-622 chip in the following applications: · SONET/SDH Add/Drop Multiplexers · SONET/SDH Terminal Multiplexers · SONET/SDH Digital Cross-Connects
· Channelized Routers and Switches
TYPICAL APPLICATIONS
STS-12/STM-4 AGGREGATE INTERFACE WITH TRIBUTARY POINTER PROCESSING AND PERFORMANCE MONITORING
622 Mbit/s Optical Interface Optical Transceiver
PM5313 SPECTRA-622
AC1J1V1[1] AD[7:0], ADP[1] APL[1] ACK PM5363 TUPP+622 IC1J1[1] OC1J1V1[1] ID[7:0], IDP[1] OD[7:0], ODP[1] IPL[1] OPL[1] HSCLK Drop
77.76 MHz 8-Bit High-Speed Telecombus Interface
DC1J1V1[1] RXD +/- DD[7:0], DDP[1] SD DPL[1] TXD +/DCK
Add
CHANNELIZED OC-12 INTERFACE FOR HIGH SPEED ROUTERS
Channelized OC-12 Card 622 Mbit/s Optical Interface Opt SPECTRA622 Opt
S/UNI QJET S/UNI QJET S/UNI QJET
FREEDM-8
FREEDM-8
FREEDM-8
FREEDM-8
Bus Interface
FREEDM-8
FREEDM-8
Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200
To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator
All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com
PMC-1981271 (R4) 2001 PMC-Sierra, Inc. FREEDM-8 is a trademark of PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT'S CUSTOMERS' INTERNAL USE
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