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Details, datasheet, quote on part number:PM7389
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| Part: | PM7389 |
| Category: | Communication => Network => Network Processors => Packet Processors |
| Description: | Frame Engine And Datalink Manager |
| Company: | PMC-Sierra |
| Datasheet: | Download PM7389 datasheet File size : 61 kB |
| Request For quote: | Find where to buy PM7389
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Datasheet text preview:
Preliminary
PM7389 FREEDM 84A1024
Frame Engine and Datalink Manager
FEATURES
· Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s. · Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. · Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. · Supports up to 42 multilink bundles with up to 12 member links per bundle. These bundles are composed of independent HDLC channels. · Support for up to 100ms of intra bundle skew in the receive direction when supporting the minimum fragment size. · Support for PPP header compression as per RFC 1661. · Link Control protocol packets are identified by the PID as control protocols and will be forwarded to the Any-PHY interface.
FRAME RELAY
· Link layer address lookup can be performed based on HDLC channel and 10 bit DLCI for HDLC channels supporting Frame Relay protocols. · The lookup algorithm can support a maximum of 16 K connection identifiers (CIs) amongst multilink FR bundles. The connection identifiers are ignored in singlelink FR channels. · Control frames are identified and forwarded to Any-PHY interface. · 12 bit sequence numbers supported. · FECN, BECN, and DE ingress processing as per FRF.12.
MULTILINK PPP AND FRAME RELAY BUNDLES
· Capable of supporting fragment sizes from 1 to 9.6 Kbytes.
PPP
· Support for 16 COS levels in accordance with RFC 2686. · Either 12 bit or 24 bit sequence number, with short and long fragment header formats, is supported.
BLOCK DIAGRAM
BCLK AD[31:0] ADSB CSB WR BURSTB BLAST READYB BTERMB WRDONEB INTHIB INTLOB BUSPOL RSTB PMCTEST SCAN_EN DLLTEST SYSCLK
TCLK[0] TCLK[4] TCLK[8] TD[0] TD[4] RD[8]
TDO TDI TCK TMS TRSTB
DDLL140
JTAG
Microprocessor I/F (BUMP2) T x ANY-PHY I/F (TAPI-12) Egress Queue Manager (EQM-12) Tx Fragment Builder (TFRAG) SRAM Controller (SRAMC)
ACIFP CIFPOUT ADATA[7:0] A DP APL AV5 AJUST_REQ AACTIVE ADETECT[1:0]
Insert SBI (INSBI)
T ransmit Channel Assigner (T CAS-12)
Tx HDLC Processor / Partial Packet Buffer (THDL-12)
TXCLK TXADDR[15:0] TPA TXDATA[15:0] TXPRTY TRDY TSX TEOP TMOD TERR CCDAT[35:0] CCADD[17:0] CCW E B CCSELB CCBSELB[1:0] CBDAT[47:0] CBADD[12:0] CBW EB CBCSB CBRASB CBCASB CBBS[1:0] RXCLK RXADDR[3:0] RPA RENB RXDATA[15:0] RXPRTY RVAL RSX RSOP REOP RMOD RERR
Performance Monitor (PM-12)
REFCLK Rx HDLC Processor / Partial Packet Buffer (RHDL-12)
CB DRAM Controller (CB_DRAMC)
DDATA[7:0] DDP DPL DV5 DC1FP Extract SBI (EXSBI) Receive Channel Assigner (RCAS-12)
Rx Fragment Builder (RFRAG)
Frame Builder (FRMBLD)
Ingress Queue Manager (EQM-12) Rx ANY-PHY I/F (RAPI-12)
RS DRAM Controller (RS_DRAMC)
RSDAT[31:0] RSADD[12:0] RSWEB RSCSB RSRASB RSCASB RSBS[1:0] DQM
RCLK[0] RCLK[4] RCLK[8] RD[0] RD[4] RD[8]
Data Control
PMC-1991477 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
© Copyright PMC-Sierra, Inc. 2001
Preliminary PM7389 FREEDM 84A1024
Frame Engine and Datalink Manager
HDLC
· Support for up to 1024 bidirectional HDLC channels, with individual HDLC channel speeds ranging from 56 Kbit/s to 52 Mbit/s. In a channelized application, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1). · The 1024 HDLC channels can be assigned to a mixture of physical links via the 19.44 MHz SBI interface. The SBI transports the equivalent of 3 STS1 synchronous payload envelopes (SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s, 21 E1s or 1 DS3. · For each channel, supports programmable flag sequence detection and generation, bit stuffing and destuffing, and validation and generation of either CRC-CCITT or CRC-32 frame check sequences. · For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. · A 100 MHz, 32-bit SDRAM interface for ingress re-sequencing data. structures. · A 100 MHz, 36-bit SSRAM interface for Ingress/Egress Context storage. · Provides a standard 5 signal P1149.1 JTAG test port for boundary scan. · A 32-bit microprocessor interface for configuration and status monitoring.
INTERFACES
· 52 MHz 16 bit Any-PHY Level 2 packet interface for transfer of packet, frame or fragment data using an external controller. The interface is capable of supporting full datagram transfer on a per Any-PHY channel basis, or fragmented packets or frames on a per Any-PHY channel basis. · A 19.44 MHz SBI bus supporting up to 84 links. · 3 separate clock and data interfaces to support 3 links of arbitrary data rate up to 52 MHz (e.g., DS3/E3). The device can be configured to process data from either the clock and data interfaces or from the SBI on a per clock-datalink/SPE basis. · A 100 MHz, 48-bit SDRAM interface for ingress and egress per packet/fragment storage.
TECHNOLOGIES
· 40 mm x 40 mm, 520 pin (1.27 mm pitch) enhanced ball grid array (SBGA) package. · Low power 0.18 mm CMOS technology using 1.8 V core power and 3.3 V I/O.
APPLICATIONS
· IETF PPP interfaces for routers. · Frame Relay interfaces for ATM or Frame Relay switches and multiplexers. · Internet/Intranet access equipment.
TYPICAL APPLICATION
OC-12 MULTISERVICE ARCHITECTURE
TelecomBus SBI Any-PHY (Packet) Any-PHY (Cell)
PM831 6 TEMUX-84
PM738 9 FREEDM84A1024
P a c k e t/Ce l l Internetworking F unc tion
PM8316 TEMUX-84 PM531 3 SPECTRA622 PM8316 TEMUX-84
PM7341 S/UNI-IMA84
Any-PHY
APPI
PM7326 S/UNI-APEX
OC-12
PM731 22 PMA3122 torA 7 L1ga PM73122 orAAL1gat2 3 AAL1gator32 32
PM7324 S/UNIATLAS
H-MVIP PM8316 TEMUX-84
VoATM DSP
Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200
To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator
All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com
PMC-1991477 (r2) © Copyright PMC-Sierra, Inc. 2001. All rights reserved. S/UNI is a registered trademark of PMC-Sierra. Any-PHY, SPECTRA-622, TEMUX-84, FREEDM-84A1024, AAL1gator, SBI, and PMC-Sierra are trademarks of PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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