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Details, datasheet, quote on part number:2DAC-C16R
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Features
New Product Development Integrated Passive Device ESD Protection to IEC61000-4-2 Spec.
2DAC-C16R Series - Integrated Passive & Active Device using CSP
General Information This application specific integrated passive component is designed to provide all of the necessary ESD protection on the data port of a portable electronic device. The ESD protection provided by the component enables the data port to withstand ±8 KV Contact / ±15 KV Air Discharge when tested according to the method specified in IEC 61000-4-2. The component incorporates 12 identical ports and is supplied in a 16 pin CSP package which is intended to be mounted directly onto an FR4 printed circuit board. This package is designed to meet typical thermal cycle and bend test specifications without the use of an underfill material.
SOLDER BUMPS SILICON DIE
Figure 1 CSP Format
Electrical & Thermal Characteristics
Electrical Characteristics
(TA = 25 °C unless otherwise noted) Zener Diode Breakdown Voltage @ 1 mA Leakage Current @ 3 V Diode Capacitance @ 1 V & 1 MHz ESD Performance (Note 1 & 2) Withstand Contact Discharge Air Discharge Let Through Contact Discharge Air Discharge
Symbol
VZT IR CT
Minimum
6 8.5
Nominal
7.2 10.5
Maximum
8 1 12.5
Unit
V uA pF
±8 ±15 ±150 ±150
kV kV V V
Thermal Characteristics
(TA = 25 °C unless otherwise noted) Operating Temperature Storage Temperature Total Power Dissipation @ 70 °C Note: TJ Tstg PD -40 -60 25 25 +85 +125 100 °C °C mW
1. The IEC 61000-4-2 test method will be adapted for component level testing. The device will provide the specified ESD protection performance on the "EXT1 12" pins only. 2. "Let Through" is a measure of the component of an incident ESD transient that the protection device allows through to the down stream circuitry.
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
2DAC-C16R Series - Integrated Passive & Active Device using CSP
Mechanical Characteristics This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die, provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is 0.5 mm. The dimensions for the CSP packaged device are shown in Fig. 2 below.
BUMP A1/PIN 1 INDICATOR 858 ± 40 (33.78 ± 1.57) 248.5 ± 45 (9.78 ± 1.78)
428.5 ± 45 (16.87 ± 1.78)
A1
B1
C1
D1
A2
B2
C2
D2
500 (19.69)
A3 B3
300 DIA. (11.81)
C3 D3
2177 ± 45 (85.71 ± 1.78) BOURNS LOGO
500 (19.69)
A4 B4 C4 D4
225 ± 20 (8.86 ± 0.79)
248.5 ± 45 (9.78 ± 1.78)
45 ± 45 (1.78 ± 1.78) 1997 ± 45 (78.62 ± 1.78)
45 ± 45 (1.78 ± 1.78)
DIMENSIONS =
MICRONS (MILS)
Fig. 2 Device Mechanical Drawing
Reliability Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices using CSP packaging. "Package level" testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2DAC-C16R and is thus deemed a worse case for Thermal Cycle testing. "Silicon level" reliability performance will be assured by similarity to other Integrated Passive and Active Devices using CSP product from Bourns.
Individual Channel Schematic This section contains the schematic (See Fig. 3 below) for the single channel in the integrated passive device. Note that the electrical parameter of primary interest is the ESD performance. Key Design Parameters Zener Diode VBR: 6 V Min, 8 V Max @ IBR = 1 mA IR: 1 uA Max @ VR = 3 V CT: 8.5 pF Min, 10.5 pF Typ, 12.5 pF Max @ VR = 1 V & F = 1 MHz
EXT1-12
±6.5 V
GROUND
Fig. 3 Channel Schematic
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
2DAC-C16R Series - Integrated Passive & Active Device using CSP
Block Diagram Figure 4 contains a block diagram of the CSP device. This diagram includes the pin names and basic electrical connections associated with each channel. Marking The device will be laser marked on the backside according to the following Fig. 5 scheme below. Position A1, on the Bump Grid is located at the top left of the die when the die is orientated so that the mark is read in the normal fashion.
PIN A1 LOCATION GROUND
EXT1 ±6.5 V GROUND ±6.5 V
EXT12
1
2
3
4
A B C D
DAC Lotcode
EXT2 ±6.5 V ±6.5 V
EXT11
Fig. 5 Backside Laser Mark
EXT3 ±6.5 V ±6.5 V EXT10
PCB Design and SMT Processing Please consult Bourns' Thin Film on Silicon using CSP Users Guide Application Note for notes on PCB design and SMT processing.
EXT4 ±6.5 V ±6.5 V
EXT9
How to Order
EXT5 ±6.5 V ±6.5 V EXT8
2 DAC - C16R__
Thinfilm Model Chipscale No. of Solder Bumps Packaging Option - R = Tape and Reel Packaged 3000 pcs. / 7 " reel
EXT6 ±6.5 V GROUND ±6.5 V
EXT7
GROUND
Fig. 4 Device Block Diagram
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
2DAC-C16R Series - Integrated Passive & Active Device using CSP
Device Pin Out The Pin-Out for the device is shown in Fig. 6. Note also that the device is shown with bumps facing up.
EXT10 EXT4 EXT8
D
EXT11 EXT7
C
EXT12
B
EXT1 EXT6
GROUND X4
A
EXT2
Pin A1 A2 A3 A4 B1 B2 B3 B4
Name EXT2 EXT3 EXT4 EXT5 EXT1 GND GND EXT6
Pin C1 C2 C3 C4 D1 D2 D3 D4
Name EXT12 GND GND EXT7 EXT11 EXT10 EXT9 EXT8
Fig. 6 (b) - Pin Listings
1
EXT3
2
3
EXT4
4
EXT5
Fig. 6 (a) - Device Pin Out "Bumps Up" View
Packaging The product will be dispensed in an 8mm x 4mm Tape and Reel format - see Fig. 7 diagram below. The Tape and Reel package will conform to customer specification.
0.3 ± 0.05 (.01 ± .002) 2.0 ± 0.05 (.08 ± .002) 4.0 ± 0.1 (.16 ± .004) 1.5 ± 0.1/-0 (.06 ± .004/-0) DIA. 1.75 ± 0.1 (.07 ± .004)
R
0.3 MAX. (0.01)
8.0 ± 0.3 (.31 ± .01) 3.5 ± 0.05 (.14 ± .002) 2.12 ± 0.05 (.08 ± .002) 4.0 ± 0.1 (.16 ± .004) R 0.25 TYP. (0.001) DIMENSIONS = MILLIMETERS (INCHES)
0.90 ± 0.05 (.04 ± .002)
2.30 ± 0.05 (.09 ± .002)
ORIENTATION OF COMPONENT IN POCKET BACKSIDE FACING UP
Fig. 7 - Tape and Reel Drawing
Reliable Electronic Solutions
Asia-Pacific: TEL +886- (0)2 25624117 · FAX +886- (0)2 25624116 Europe: TEL +353 214 515 225 · FAX +353 214 515 292 North America: TEL +1-909 781-5492 · FAX +1-909 781-5700
www.bourns.com
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
COPYRIGHT© 2002, BOURNS, INC. LITHO IN U.S.A. 9/02 e/TF0206rev 2DAC-C16R 8/12/03
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