|Category||Interface and Interconnect|
|Description||Low-side And High-side Drive With Simultaneous Conduction Lockout|
|Company||Power Integrations, Inc.|
|Datasheet||Download INT100 datasheet
|Low-Side and High-side Drive with Simultaneous Conduction Lockout
5 V CMOS Compatible Control Inputs Combines logic inputs for low and high-side drives Schmidt-triggered inputs for noise immunity Built-in High-voltage Level Shifters Can withstand 800 V for direct interface to the HVreferenced high-side switch Pulsed internal high-voltage level shifters reduce power consumption Gate Drive Outputs for External MOSFETs Provides sink/150 mA source current Can drive MOSFET gates 15 V External MOSFET allows flexibility in design for various motor sizes Built-in Protection Features Simultaneous conduction lockout protection Undervoltage lockoutDescription
The INT100 half-bridge driver IC provides gate drive for external low-side and high-side MOSFET switches. The INT100 provides a simple, cost-effective interface between low-voltage control logic and high-voltage loads. The INT100 is designed to be used with rectified 220 V supplies. Both highside and low-side switches can be controlled independently from ground-referenced 5 V logic inputs. Built-in protection logic prevents both switches from turning on at the same time and shorting the high voltage supply. Pulsed internal level shifting saves power and provides enhanced noise immunity. The circuit is powered from a nominal 15 V supply to provide adequate gate drive for external N-channel MOSFETs. A floating high-side supply is derived from the low-voltage rail by using a simple bootstrap technique. Applications for the INT100 include motor drives, electronic ballasts, and uninterruptible power supplies. Multiple devices can also be used to implement full-bridge and multi-phase configurations. The INT100 is available a 16-pin plastic SOIC package.PART NUMBER INT100S PACKAGE OUTLINE S16A ISOLATION VOLTAGE 800 V
Pin 1: VDD supplies power to the logic, highside interface, and low-side driver. Pin 2: Active-low logic level input HS IN controls the high-side driver output. Pin 3: Active-high logic level input LS IN controls the low-side driver output. Pin 4, 5: COM connection is used as the analog reference point for the circuit. Pin 7: LS RTN is the power reference point for the low-side circuitry, and should be connected to the source of the low-side MOSFET and to the COM pin. Pin 8: LS OUT is the driver output which controls the low-side MOSFET. Pin 11: HS OUT is the driver output which controls the high-side MOSFET. Pin 12,13,14: HS RTN is the power reference point for the high-side circuitry, and should be connected to the source of the high-side MOSFET. Pin 15: VDDH supplies power to the high-side control logic and output driver. This is normally connected to a high-side referenced bootstrap circuit or can be supplied from a separate floating power supply.
5 V Regulators Both low-side and high-side driver circuits incorporate 5 V linear regulator circuit. The low-side regulator provides the supply voltage for the control logic and high-voltage level shift circuit. This allows HS IN and to be directly compatible with 5 V CMOS logic without the need of an external 5 V supply. The high-side regulator provides the supply voltage for the noise rejection circuitry and high-side control logic. Undervoltage Lockout The undervoltage lockout circuit for the low-side driver disables both the LS OUT and HS OUT pins whenever the VDD power supply falls below typically 9.0 V, and maintains this condition until the V DD power supply rises above typically 9.35 V. This guarantees that both MOSFETs will remain off during power-up or fault conditions. The undervoltage lockout circuit for the high-side driver disables the HS OUT pin whenever the VDDH power supply falls below typically 9.0 V, and maintains this condition until the VDDH power supply rises above typically 9.35 V. This guarantees that the high-side MOSFET will be off during power-up or fault conditions. Level Shift The level shift control circuitry of the low-side driver is connected to integrated high-voltage N-channel MOSFET transistors which perform the levelshifting function for communication to the high-side driver. Controlled current capability allows the drain voltage to float with the high-side driver. Two individual channels produce a true differential communication channel for accurately controlling the high-side driver in the presence of fast moving high-voltage waveforms. The high voltage level shift transistors employed exhibit very low output capacitance, minimizing the displacement currents between the low-side and high-side drivers during fast moving voltage transients created during switching of the external MOSFETs. As a result, power dissipation is minimized and noise immunity optimized. The pulse circuit provides the two highvoltage level shifters with precise timing signals. These signals are used by the discriminator to reject spurious noise. The combination of differential communication with the precise timing provides maximum immunity to noise. Simultaneous Conduction Lockout A latch prevents the low-side driver and high-side driver from being on at the same time, regardless of the input signals. Delay Circuit The delay circuit matches the low-side propagation delay with the combination of the pulse circuit, high voltage level shift, and high-side driver propagation delays. This ensures that the low-side driver and high-side driver will never on at the same time during switching transitions in either direction. Driver The CMOS drive circuitry on both lowside and high-side driver ICs provide drive power to the gates of the external MOSFETs. The drivers consist of a CMOS buffer capable of driving external transistor gates 15 V.
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