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Part: QL3006-1PL68C
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Pasic High-Speed, Low Power, Instant-On, High Security Fpgas
Company: QuickLogic Corp
Datasheet: Download QL3006-1PL68C datasheet File size : 562 kB
Request For quote: Find where to buy QL3006-1PL68C
Datasheet text preview:
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6,000 Usable PLD Gates with 82 I/Os 300 MHz 16-bit Counters,
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Two array clock/control networks available
400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes
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100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset inputs -- each driven by an input-only pin Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs and the data input, I/O register clock, reset and enable inputs as well as the output enable control -- each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback
complete pin-out stability Variable-grain logic cells provide high performance and 100% utilization Comprehensive design tools include high quality Verilog/VHDL synthesis
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Input + logic cell + output total delays
under 6 ns Data path speeds over 400 MHz Counter speeds over 300 MHz
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Inter faces with both 3.3 V and 5.0 V devices PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades Full JTAG boundary scan I/O Cells with individually controlled Registered Input Path and Output Enables
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74 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades Four High Drive input-only pins Four High Drive input-only/distributed network pins
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The QL3006 is a 6,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3006 contains 160 logic cells. With a maximum of 82 I/Os, the QL3006 is available in 68-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages. Software support for the complete pASIC 3 family, including the QL3006, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
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