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Details, datasheet, quote on part number:QL3012
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| Part: | QL3012 |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) |
| Description: | Pasic High-Speed, Low Power, Instant-On, High Security Fpgas |
| Company: | QuickLogic Corp |
| Datasheet: | Download QL3012 datasheet File size : 356 kB |
| Request For quote: | Find where to buy QL3012
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Datasheet text preview:
QL3012 pASIC 3 FPGA Data Sheet
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12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
· 12,000 Usable PLD Gates with 118 I/Os · 300 MHz 16-bit Counters,
Four Low-Skew Distributed Networks
· Two array clock/control networks available
400 MHz Datapaths · 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes
Easy to Use / Fast Development Cycles
· 100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset inputs -- each driven by an input-only pin · Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control -- each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
complete pin-out stability · Variable-grain logic cells provide high performance and 100% utilization · Comprehensive design tools include high quality Verilog/VHDL synthesis
High Performance
· Input + logic cell + output total delays
under 6 ns · Data path speeds over 400 MHz · Counter speeds over 300 MHz
Advanced I/O Capabilities
· Inter faces with both 3.3 V and 5.0 V devices · PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades · Full JTAG boundary scan · I/O Cells with individually controlled Registered Input Path and Output Enables
Total of 118 I/O Pins
· 110 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades · Four High Drive input-only pins · Four High Drive input-only/distributed network pins
Figure 1: 320 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3012 pASIC 3 FPGA Data Sheet Rev E
Architecture Overview
The QL3012 is a 12,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3012 contains 320 logic cells. With a maximum of 118 I/Os, the QL3012 is available in 84-pin PLCC, 100-pin TQFP, and 144-pin TQFP packages. Software support for the complete pASIC 3 family, including the QL3012, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
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© 2002 QuickLogic Corporation
QL3012 pASIC 3 FPGA Data Sheet Rev E
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided in Table 1 through Table 5.
Table 1: Logic Cells Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay Setup Time b Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
b
Propagation Delays (ns) Fanouta 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7. b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 2: Input-Only/Clock Cells Symbol Parameter 1 tIN tINI tISU tIH tlCLK tlRST tlESU tlEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout a 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7.
© 2002 QuickLogic Corporation
www.quicklogic.com · ·
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