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Details, datasheet, quote on part number:V292PBC-33
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Datasheet text preview:
VxxxPBC Rev. B2
LOCAL BUS TO PCI BRIDGE CONTROLLERS Data Sheet Addendum
· Large, 576-byte FIFOs using V3's unique DYNAMIC BANDWIDTH ALLOCATIONTM architecture · 33MHz and 40MHz local bus versions available with independent PCI operation up to 33MHz · Both target and master (primary or secondary) modes supported on the PCI and local buses · Dual bi-directional address space remapping · On-the-fly byte order (endian) conversion including automatic endian detection
· I2OTM ready hardware messaging unit · 2 channel DMA controller · Bi-directional mailboxes w/doorbell interrupts · Flexible PCI and local interrupt management · Serial EEPROM configuration interface · Fully compliant with PCI 2.1 specification · Low cost 160-pin EIAJ PQFP package
This addendum is a companion to the V960PBC, V961PBC, V962PBC, V292PBC data sheets revision 2.3, which updates product codes and local bus timing parameters for revision B2 devices. The pinouts, package mechanical information, DC characteristics, and PCI bus AC characteristics for a n y of the VxxxPBC devices can be found in corresponding B1 data sheets. Detailed functional information is contained in the PBC family User's Manual. The B2 Enhancement document, which is describing the added I2O features, can be ordered by contacting V3 Semiconductor Sales office.
V3 Semiconductor retains the rights to change documentation, specifications, or device f u nc t io n a l it y at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
1.0 Product Codes
Table 1: Product Codes
Product Code V962PBC-33 REV B2 V962PBC-40 REV B2 V961PBC-33 REV B2 Processor i960Cx /Hx i960Cx /Hx i960JA/JD/JF PP C401G F i960JA/JD/JF PP C401G F i960SA/SB Bus Type P ackage F req u ency 3 3MHz 4 0MHz 3 3MHz
32-bit demultiplexed 160-pin EIAJ PQFP 32-bit demultiplexed 160-pin EIAJ PQFP 32-bit multiplexed 160-pin EIAJ PQFP
V961PBC-40 REV B2 V960PBC-33 REV B2
32-bit multiplexed 16-bit multiplexed
160-pin EIAJ PQFP 160-pin EIAJ PQFP
4 0MHz 3 3MHz 3 3MHz 4 0MHz
V292PBC-33 REV B2 Am29030/35/40 32-bit demultiplexed 160-pin EIAJ PQFP V292PBC-40 REV B2 Am29030/35/40 32-bit demultiplexed 160-pin EIAJ PQFP
Copyright © 1997, V3 Semiconductor Inc.
VxxxPBC Rev B2 Data Sheet Addendum
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V3 Semiconductor reserves the right to change the specifications of this product without notice. V962PBC, V961PBC, V960PBC and V292PBC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
VxxxPBC Rev B2 2.0 Local Bus Timings
Table 2: Local Bus AC Test Conditions
S ymb o l VCC VIN COUT Paramet e r Supply voltage Input low and high voltages Capacitive load on output and I/O pins Limits 4.75 to 5.25 0.4 and 2.0 50 Units V V pF
Table 3: Capacitive Derating for Output and I/O Pins
Output Drive Limit 4m A Deratin g 0.096 ns/pF for loads > 50pF
Figure 1: Clock and Synchronous Signals
TC TC H TS U TH TC L
LOCAL CLOCK INPUT SETUP/HOLD OUTPUT VALID
Tc z o ALID TC O V
VALID V
TC O Z VALID
OUTPUT DRIVE OUTPUT FLOAT
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VxxxPBC Rev B2 Data Sheet Addendum
Copyright © 1997, V3 Semiconductor Inc.
VxxxPBC Rev B2
Table 4: V962PBC Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33M Hz # 1 2 3 4 4a 4b 4c 4d Symbol TC TCH TCL TSU TSU TSU TSU TSU TSU TH TCOV TCOV TCZO TCOZ TRST LCLK period LCLK high time LCLK low time Synchronous input setup Synchronous input setup (BLAST) Synchronous input setup (W/R, BTERM) Synchronous input setup (ADS) Synchronous input setup (address, data, byte enables) Synchronous input setup for read data when in local bus master mode Synchronous input hold LCLK to output valid delay LCLK to output valid delay (address, data, byte enable, parity) LCLK to output driving delay LCLK to high impedance delay Reset period when LRST used as input 4 3 3 3 3 3 16· T C 1 1 2 Description No tes Min 30 12 12 7 8 4 6 9 Max 40MHz Min 25 11 11 6 7 4 5 8 Max Units ns ns ns ns ns ns ns ns
4e 5 6 6a 7 8 9
5 1 14 15 15 15
5 1 3 3 3 3 16·TC 12 14 14 14
ns ns ns ns ns ns ns
Notes: 1. Measured at 1.5V. 2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e. 3. All local bus signals except those in 6a. 4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Copyright © 1997, V3 Semiconductor Inc.
VxxxPBC Rev B2 Data Sheet Addendum
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