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Part: dac1243x
Category:
ASICs
-> Mixed Signal Cores->0.25um
Description: Description = DAC1243X 10BIT 300MSPS Triple-dac ;; Function = DAC ;; Configuration = 10BIT 300MSPS ;; Library Type = - ;; Characteristic = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download dac1243x datasheet File size : 846 kB
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Datasheet text preview:
DAC1243X
0.25µm 10-BIT 300MSPS TRIPLE DAC
GENERAL DESCRIPTION
This core dac1243x is a triple high speed, digital-to-analog converter. It consists of three high speed, 10-bit, video D/A converter. Its maximum conversion rate is 300MHz.
FEATURES
-- 300MSPS Throughput -- Tripe 10-Bit D/A Converters -- SFDR
64dB at Fclk= 300Mhz; Fout=1Mhz 56dB at Fclk= 300Mhz; Fout=6Mhz
-- +2.5V power supply -- Optional 7.5IRE(40mV) selection -- Compatible with RS-343A output level -- 10bit Voltage parallel Input -- Guaranteed monotonic to 10bit -- Commercial temperature range
TYPICAL APPLICATIONS
-- Image Processing -- High Resolution color graphic. -- Digital TV
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0.25µm 10-BIT 300MSPS TRIPLE DAC µ
DAC1243X
FUNCTIONAL BLOCK DIAGRAM
5
binary LSBs segmented MSBs 7 . 5 I R E generator
DR[9:0]
digital decode
5 1
IOR
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binary LSBs segmented MSBs 7 . 5 I R E generator
DG[9:0]
digital decode
5 1
IOG
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binary LSBs segmented MSBs 7 . 5 I R E generator
DB[9:0]
digital decode
5 1
IOB
SLEEP CLK BLANKEN VSETUP
Reference Block 7.5IRE control
CCOMP
VREFOUT
IRSET
SENSEZ
Ver 1.9 (Apr. 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.
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DAC1243X
0.25µm 10-BIT 300MSPS TRIPLE DAC
CORE PIN DESCRIPTION
Name IOR,IOG,IOB I/O Type AO I/O Pad poa_abb Pin Description Red , Greed , Blue current outputs. these high impedance current source are capable of directly driving a double terminated 75 W coaxial cable. Red, green, blue data input. These data is latched on the rising edge of CLK. Unused data inputs should be connected to either the regular PCB power or ground plane. Video signal GREEN Digital input Video signal BLUE Digital input The rising edge of CLK latches the R,DG,DB and control signal. It is typically the pixel clock rate of the video system. Power Save Control Pin. (high active) Voltage Reference Input for DACs or voltage reference. External DC Voltage(0.7V) . Compensation pin. This is a compensation pin of the internal reference amplifier. A 0.1uF ceramic capacitor must be connected between COMP and AVDD25A. This pin should be connect to AVDD25A. A resistor (Rset) connected between this pin and GND, controls the magnitude of the full-scale video signal. external resistor connection Rset(W)= Vrefout / I(IOR or IOG or IOB) × 31.96 7.5 IRE level enable (40mV) blank level enable Digital Power (2.5V ± 5%) Digital Ground Analog Power supply (2.5V ± 5%) Analog Ground
DR~DR
DI
picc_abb
DG~DG DB~DB CLK
DI DI DI
picc_abb picc_abb picc_abb
SLEEP VREFOUT CCOMP
DI AB AB
picc_abb poa_bb poa_bb
SENSEZ IRSET
AO AB
poar50_bb poa_bb
VSETUP BLANKEN VDD25A VSS25A VDD25A1 VSS25A1
DI DI DP DG AP AG
picc_abb picc_abb vdd2t_abb vdd2t_abb vss2t_abb vss2t_abb
I/O TYPE ABBR. -- AI: Analog Input -- DI: Digital Input -- AO: Analog Output -- DO: Digital Output -- AB: Analog Bidirectional -- DB: Digital Bidirectional -- AP: Analog Power -- DP: Digital Power -- AG: Analog Ground -- DG: Digital Ground
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0.25µm 10-BIT 300MSPS TRIPLE DAC µ
DAC1243X
CORE CONFIGURATION
VDD25A1
VSS25A1
VDD25A
VSS25A
VBBA1
VBBA
DR[9:0] DG[9:0] DB[9:0]
IOR
dac1243x
IOG IOB
BLANKEN
VSETUP
SLEEP
CLK
CCOMP
SENSEZ
IRESET
VREFOUT
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DAC1243X
0.25µm 10-BIT 300MSPS TRIPLE DAC
FUNCTIONAL DESCRIPTION
This is 10bit 300MSPS digital to analog data converter and uses segment architecture for 4bits of MSB sides , binary-weighted architecture for 4bits of LSB side and master slave architecture for 2bit of LSB. it contains of First latch block, decoder block Second latch block, AMP block ,BGR block, switch buffer block, SLEEP block for power down, CM(current mirror)block and analog switch block. This core uses reference current to decide the 1LSB current size by dividing the reference current by 32times. So the reference current must be constant and the switch's physical real size can be constant by using OPA block with high DC gain. The most significant block of this core is analog switch block and it must maintain the uniformity at each switch, so layout designer must care of the matching characteristics on analog switch and CM block. And more than 80% of supply current is dissipated at analog switch block and AMP block. And it uses samsung (SEC) standard cell as all digital cell of latch ,decoder and buffer. And to adjust full current output, you must decide the "Rset" resistor value(connected to IREF pin) and "Vbias" voltage value(connected to VREFOUT pin). Its voltage output can be obtained by connecting RL1(connected to IOR,IOG,IOB pin).
Error: Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Monotonicity: A D/A converter is monotonic if the output either increases or remains constants as the digital input increases. Offset Error: The deviation of the output current from the ideal of zero is called offset error. For IO, 0mV output expected when the inputs are all 0s. Gain Errors: The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range: The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Settling Time: The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition Glitch Impulse : Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s
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