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Part: DAC1243X_AL
Category:
ASICs
-> Mixed Signal Cores->0.25um
Description: Description = DAC1243X_AL 10BIT 40MSPS Hexa-channel DAC ;; Function = DAC ;; Configuration = 10BIT 40MSPS ;; Library Type = STD110 ;; Characteristic = 2.5V/210mA(Is)
Company: Samsung Semiconductor, Inc.
Datasheet: Download DAC1243X_AL datasheet File size : 846 kB
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Datasheet text preview:
DAC1243X-AL
0.25µm 10-BIT 40MSPS HEXA CHANNEL
GENERAL DESCRIPTION
This core is a CMOS hexa-channel 10bit D/A converter for general & video. The DAC1243X-AL core is in the Samsung 0.25um 2.5V process. Digital inputs are coded as binary. Each DAC channel includes power down control and the ability sense output load. An external(optional) or 0.7V reference voltage (VBIAS) and a external resister define the full-scale current together. It uses the two of current-segment and -weighted.
FEATURES
-- Maximum conversion rate is 40MSPS -- +2.5V CMOS monolithic construction -- ±0.75LSB differential linearity (typical) -- ±1.0LSB integral linearity (typical) -- External or internal voltage reference (Including Band Gap Reference Block) -- Hexa Channel DAC -- 10-Bit parallel Straight Binary Digital input per channel -- DAC auto-load detection circuitry -- Temperature: 0 ~ 70°C -- Each channel Power_Down
TYPICAL APPLICATIONS
-- High Definition Television(HDTV) -- High Resolution Color Graphics -- Hard Disk Driver (HDD) -- CAE/CAD/CAM -- Image Processing -- Instrumentation
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0.25µm 10-BIT 40MSPS HEXA CHANNEL µ
DAC1243X-AL
FUNCTIONAL BLOCK DIAGRAM
IO1 IO2 IO3 IO4 Segmented MSBs Digital Decode Binary Weighted LSBs Segmented MSBs Digital Decode Binary Weighted LSBs Segmented MSBs Digital Decode Binary Weighted LSBs IO5 IO6 Segmented MSBs Binary Weighted LSBs Segmented MSBs Binary Weighted LSBs Segmented MSBs Binary Weighted LSBs Digital Decode Digital Decode Digital Decode
D1[9:0] PDAC[0]
D6[9:0] PDAC[5]
D2[9:0] PDAC[1]
D5[9:0] PDAC[4]
D3[9:0] PDAC[2]
D4[9:0] PDAC[3]
CLK DTOUT PRE SEL ALLPD Bias_ gen Auto-load Detect CCOMP VBIAS IREF
VDD25AA1,VDD25AD1 VSS25AA1,VSS25AD1 VABB
Ver 1.3 (Aug. 2000) This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.
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DAC1243X-AL
0.25µm 10-BIT 40MSPS HEXA CHANNEL
PIN CONFIGURATION
Name PDAC[5:0] CLK PRE I/O Type DI DI DI I/O Pad piar50_abb picc_abb piar50_abb Pin Description Individual DAC power down control. When activated (high), the corresponding DAC is disabled. DAC master clock. Input data is sampled with the rising edge of CLK. Control strobe for the DAC auto-load detection comparator. When PRE transitions high-to-low, the auto-load detect circuit evaluates its selected input. Appropriate settling time must be allowed before the comparator output (DTOUT) is used. When not used, PRE should be left high. 10-bit straight binary digital input for each DAC channel.
D1[9:0] D2[9:0] D3[9:0] D4[9:0] D5[9:0] D6[9:0] ALLPD
DI
picc_abb
DI
piar50_abb
Power down control for Bandgap and all six DACs. A high level disables all six DACs plus the bandgap reference regardless of the states of PDAC0-5 Comparator output for detection of resistive load at DAC output. A low at the detect output indicates that the output voltage of the selected channel is above 0.53V and therefore that no load is attached. Internal DAC compensation node. Connect external 0.1uF cap to VDD25AA1. External resistor from this node to VSS25AA1 defines the full scale output current for the DACs. External reference voltage output.
DTOUT
DO
pot8_abb
CCOMP IRSET VBIAS
AB AB AB
poa_bb poa_bb poa_bb
I/O TYPE ABBR. -- AI: Analog Input -- DI: Digital Input -- AO: Analog Output -- DO: Digital Output -- AB: Analog Bidirectional -- DB: Digital Bidirectional -- AP: Analog Power -- DP: Digital Power -- AG: Analog Ground -- DG: Digital Ground
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0.25µm 10-BIT 40MSPS HEXA CHANNEL µ
DAC1243X-AL
Name VDD25AA1 VSS25AA1 VDD25AD1 VSS25AD1 VABB IO1 IO2 IO3 IO4 IO5 IO6 I/O TYPE ABBR. -- AI: Analog Input -- DI: Digital Input -- AO: Analog Output -- DO: Digital Output
I/O Type AP AG DP DG AG AO AO AO AO AO AO
I/O Pad vdd2t_bb vss2t_abb vdd2t_abb vss2t_abb vbb_abb poa_bb poa_bb poa_bb poa_bb poa_bb poa_bb
Pin Description Analog Power (needs 3 pads) Analog Ground (needs 3 pads) Digital Power Digital Ground Substrate Bias(the same with ground level) 1st Analog Current Output 2nd Analog Current Output 3rd Analog Current Output 4th Analog Current Output 5th Analog Current Output 6th Analog Current Output
-- AB: Analog Bidirectional -- DB: Digital Bidirectional -- AP: Analog Power -- DP: Digital Power -- AG: Analog Ground -- DG: Digital Ground
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DAC1243X-AL
0.25µm 10-BIT 40MSPS HEXA CHANNEL
CORE CONFIGURATION
VDD25AA1
VSS25AA1
VDD25AD1
VSS25AD1
VBBA
IO1 D1[10:0]
IO2
D2[10:0] IO3 D3[10:0]
Dac1243x-al
IO4 IO5
D4[10:0]
D5[10:0]
D6[10:0] IO6
ALLPD PDAC[6::1]] CLK P C50
PRE
SEL[2:0]
DTCT_OUT CCOMP IRSET VBIAS DTOUT
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