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Details, datasheet, quote on part number:dac1243x_sr
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| Part: | dac1243x_sr |
| Category: | ASICs => Mixed Signal Cores->0.25um |
| Description: | Description = DAC1243X_SR 10BIT 30MSPS Single Channel DAC DAC1243X_SR ;; Function = DAC ;; Configuration = 10BIT 30MSPS ;; Library Type = STD110 ;; Characteristic = 2.5V/38mA(Is) |
| Company: | Samsung Semiconductor, Inc. |
| Datasheet: | Download dac1243x_sr datasheet File size : 135 kB |
| Request For quote: | Find where to buy dac1243x_sr
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Datasheet text preview:
DAC1243X-SR
0.25µm 10-BIT 30MSPS SINGLE CHANNEL DAC
GENERAL DESCRIPTION
This core is a CMOS single-channel 10bit 30MSPS D/A converter for general & video applications. The dac1243x_sr core is implemented in the Samsung 0.25um 2.5V CMOS process. Digital inputs are coded with straight binary. This DAC includes independent power down control and the ability to sense output load. An external(optional) or internal 0.7V reference voltage(VBIAS) and a single external resister define the full-scale output current together. It uses the two architecture of current-segment and binary-weighted.
FEATURES
-- Maximum conversion rate is 40MSPS -- +2.5V CMOS monolithic construction -- ±0.75LSB differential linearity (typical) -- ±1.0LSB integral linearity (typical) -- External or internal voltage reference (Including Band Gap Reference Block) -- Single Channel DAC -- 10-Bit parallel Straight Binary Digital input -- DAC auto-load detection circuitry -- Temperature : 0 ~ 70°C -- Just analog switch power_down enable
TYPICAL APPLICATIONS
-- High Definition Television(HDTV) -- High Resolution Color Graphics -- Hard Disk Driver (HDD) -- CAE/CAD/CAM -- Image Processing -- Instrumentation
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0.25µm 10-BIT 30MSPS SINGLE CHANNEL DAC µ
DAC1243X-SR
FUNCTIONAL BLOCK DIAGRAM
Segmented MSBs D1[9:0] PDAC Digital Decode Segmented MSBs
IO1 VSS25AA1,VSS25AD1
VDD25AA1,VDD25AD1
DTOUT PRE SEL ALLPD Bias_gen
Auto-load Detect CCOMP VBIAS IREF
Ver 1.2 (Sep. 2000) This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.
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DAC1243X-SR
0.25µm 10-BIT 30MSPS SINGLE CHANNEL DAC
PIN CONFIGURATION
Name PDAC CLK PRE I/O Type DI DI DI I/O Pad piar50_abb picc_abb piar50_abb Pin Description Power down control just for Analog Switch Block When activated(high) all current switches are disabled. DAC master clock. Input data is latched into the DACs on the rising edge of CLK. Control strobe for the DAC auto-load detection comparator. When PRE transitions high-to-low, the auto-load detect circuit evaluates its analog input. Appropriate settling time must be allowed before the comparator output (DTOUT) is used. When not used, PRE should be left high. 10-bit straight binary, parallel digital input Selection control for this DAC output as an input of auto load-detection function. Enable of load detection for the DAC is SEL=Low. Power down control for Bandgap and all blocks. A high level disables all analog switches and digital blocks plus the band gap reference regardless of the states of PDAC Comparator output for detection of resistive load at DAC output. A low at the detect output indicates that the output voltage of the current selected DAC is above 0.53V and therefore that no load is attached. Internal DAC compensation node. Connect external 0.1uF cap to VDD25AA1. External resistor from this node to VSS25AA1 defines the full scale output current for the DACs. External reference voltage output. Analog Power (2 pads for this node is recommended.) Analog Ground (2 pads for this node is recommended) Digital Power Digital Ground Substrate Bias(the same with ground level) Analog Current Output
D[9:0] SEL
DI DI
picc_abb picc_abb
ALLPD
DI
piar50_abb
DTOUT
DO
pot8_abb
CCOMP IRSET VBIAS VDD25AA1 VSS25AA1 VDD25AD1 VSS25AD1 VABB IO I/O TYPE ABBR. -- AI: Analog Input -- DI: Digital Input
AB AB AB AP AG DP DG AG AO
poa_abb poa_abb poa_abb vdd2t_abb vss2t_abb vdd2t_abb vss2t_abb vbb_abb poa_abb
-- AO: Analog Output -- DO: Digital Output -- AB: Analog Bidirectional -- DB: Digital Bidirectional -- AP: Analog Power -- DP: Digital Power -- AG: Analog Ground -- DG: Digital Ground
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0.25µm 10-BIT 30MSPS SINGLE CHANNEL DAC µ
DAC1243X-SR
CORE CONFIGURATION
VDD25AD1 VDD25AA1 VSS25AD1 VSS25AA1
VBBA
LSB D1[0] D1[1] D1[2] D1[3] D1[4] D1[5] D1[6] D1[7] D1[8] MSB D1[9]
dac1243x_sr
IO1
ALLPD
PDAC
CLK
PRE
SEL
DTOUT
CCOMP
IRSET
VBIAS
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DAC1243X-SR
0.25µm 10-BIT 30MSPS SINGLE CHANNEL DAC
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Voltage on Any Digital Pin Storage Temperature Range Symbol VDD25AA1 - VSS25AA1 VDD25AD1 - VSS25AD1 CLK Tstg Value 2.5 VSS25AD1-0.25 to VDD25AD1+0.25 -45 ~ 125 Unit V V °C
NOTES: 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to GND unless otherwise specified 3. Applied voltage must be limited to specified range.
RECOMMENDED OPERATING CONDITIONS
Characteristics Operating Supply Voltage Digital Input Voltage High Digital Input Voltage Low Operating Temperature Range Output Load(effective) Reference Load(effective) Resistor Reference Voltage Data Input Setup Time Data Input Hold Time Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low Zero_level Voltage IRSET Current Symbol VDD25AD1,VDD25AA1 VIH VIL Topr RL Rset VBIAS TS TH T CLK TPWH TP W L VOZ IREF Min 2.25 1.75 0 4 1 25 12 12 -10 0.9 Typ 2.5 2.5 0.0 25 37.5 658 0.7 -5 1.06 Max 2.75 0.75 70 +10 1.1 Unit V V V °C V ns ns ns ns ns mV mA
NOTE: It is strongly recommended that all the supply pins (VDD25AA1,VDD25AD2) be powered from the same source and all the ground pins(VSS25AA1,VSS25AD1,VABB) avoid power latch-up.
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