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Part: DAC1252X_JVC
Category:
ASICs
-> Mixed Signal Cores->0.25um
Description: Description = DAC1252X_JVC 2.5V 8BIT 2MSPS DAC DAC1252X_JVC ;; Function = DAC ;; Configuration = 8BIT 2MSPS ;; Library Type = STD110 ;; Characteristic = 2.5V/1.22mA(Isc)
Company: Samsung Semiconductor, Inc.
Datasheet: Download DAC1252X_JVC datasheet File size : 846 kB
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Datasheet text preview:
2.5V 8BIT 2MSPS DAC
GENERAL DESCRIPTION
The DAC1252X_JVC is a CMOS 8BIT D/A converter for general application. This digital to analog converter has a R2R structure. Its settling time is 500ns (Typical value).
DAC1252X_JVC
FEATURES
· · · · · · · · Resolution : 8BIT Differential Linearity Error : ± 1.0 LSB Integral Linearity Error : ± 1.0 LSB Settling Time : 500ns Low Power Consumption : 890uA Power Down Mode Operation Temperature Range : 0ºC ~ 70ºC Power Supply : 2.5V Single and 1.8V single
TYPICAL APPLICATIONS
· · · · Hard Disk Drive (HDD) Battery Operated Instruments Motor Control Systems General Applications
FU NC T IO NA L B L O CK DIA G R AM
AVDD25A
AVDD25D
AVDD18D
AVBB25A
D[7:0]
Level Shifter
AVSS25A
AVSS25D
VRT VRB
R2R
+ _ AMP
VOUT
PD
Ver 1.0 (June 2000) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
2.5V 8BIT 2MSPS DAC
CORE PIN DESCRIPTION
NAME
D[7:0] PD VRT VRB VOUT AVDD25A AVSS25A AVDD25D AVSS25D AVDD18D AVBB25A
DAC1252X_JVC
I/O TYPE
DI DI AB AB AO AP AG DP DG DP AG
I/O PAD
picc_abb picc_abb pia_abb pia_abb poa_abb vdd2t_abb vdd2t_abb vdd2t_abb vss2t_abb vss1t_abb vbb_abb
PIN DESCRIPTION
Digital Input Data (8BIT) D[7] : MSB , D[0] : LSB Power Down (Active Low) Voltage Reference Top Voltage Reference Bottom Analog Voltage Output Analog Power (+2.5V) Analog Ground (0.0V) Digital Power (+2.5V) Digital Ground (0.0V) Digital power (+1.8V) Analog Sub Bias (0.0V)
I/O TYPE ABBR.
· · · · · · · · · · AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground
CORE CONFIGURATION
AVBB25A
AVDD18D
AVDD25A
AVSS25A
D[7:0]
dac1252X_jvc
AVDD25D
AVSS25D
VOUT
VRT
VRB
PD
SEC ASIC
2 / 10
ANALOG
2.5V 8BIT 2MSPS DAC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Supply Voltage Analog Output Voltage Digital Input Voltage Reference Voltage Operating Temperature Range
DAC1252X_JVC
Symbol
VDD (AVDD25A,AVDD25D) VOUT D[7:0] VRT VRB Topr
Value
3.3 AVSS25A to AVDD25A VSS25D to AVDD18D AVDD25A AVSS25A 0 to 70
Unit
V V V V °C
NOTES : 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS(AVSS25A or VSS25AD0 or AVBB25A) unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Supply Voltage Supply Voltage Difference Reference Voltage Digital Input 'Low' Voltage Digital Input 'High' Voltage Operating Temperature
Symbol
AVDD25A - AVSS25A AVDD25D - VSS25AD0 AVDD25A - AVDD25D VRT VRB VIL VIH Topr
Min
2.375 -0.1 0.0 0.7×AVDD18D
Typ
2.5 0.0 -
Max
2.625 0.1 2.5 0.3×VDD18D
Unit
V V V
70
V °C
0
NOTE : It is strongly recommended that to avoid power latch-up all the supply pins(AVDD25A,AVDD25D) be driven from the same source.
SEC ASIC
3 / 10
ANALOG
2.5V 8BIT 2MSPS DAC
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=VSS25AD0=AVBB25A=0V, PD=High, Top=25°C, VRT=2.5V, VRB=0.0V unless otherwise specified.)
DAC1252X_JVC
Characteristics
Resolution Differential Linearity Error Integral Linearity Error Zero Scale Error1 Full Scale Voltage Error2 Maximum Output Voltage LSB Size
NOTE
Symbol
Bit DLE ILE VZSE VFSE VoMAX VLSB
Min
-
Typ
8 1.0 1.0 5 5 2.499 0.61
Max
-
Unit
Bits LSB LSB mV mV V mV -
Conditions
VRT=2.5V , VRB=0.0V VoMAX = VOUT(D[7:0]=High) VLSB = VoMAX / 256
1 : VZSE=VOUT(D[7:0]=Low) - VRB 2 : VFSE=VOUT(D[7:0]=High) - {(VRT-VRB) × 255/256 + VRB}
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=VSS25AD0=AVBB25A=0V, load cap=25pF Top=25°C, PD=High, VRT=2.45V, VRB=0.05V unless otherwise specified.)
Characteristics
Symbol
Ivdd1
Min
-
Typ
0.89
Max
-
Unit
mA
Conditions
Ivdd1 = IVDD28AA0 + IAVDD25D VRT=2.5V , VRB = 0.0V Data Input : All Low or All High Ivdd2 = IAVDD25A + IAVDD25D Data Input : All Low or All High Ivdd3 = IAVDD25A + IAVDD25D Data Rate = 2MHz Load cap = 25pF , PWDN=LOW VOUT : AVSS25A or AVDD25A Data Input : All High or All Low Data Rate = 2MHz Data : All LOW All HIGH Data Rate = 2MHz Data : All LOW All HIGH Data Rate = 2MHz Data : All HIGH All LOW Data Rate = 2MHz Data : All LOW All HIGH PD : HIGH LOW PD : LOW HIGH
Supply Current Ivdd2 Supply Current (Power Down Mode) Short Circuit Current Analog Output Delay Analog Output Rise Time Analog Output Fall Time Analog Output Settling Time Power Down Off Time Power Down On Time 1.22 mA
Ivdd3
-
-
10
uA
ISC Td Tr Tf Ts Ton Toff
-
12 65 100 100 500 500 500
-
mA ns ns ns ns ns ns
SEC ASIC
4 / 10
ANALOG
2.5V 8BIT 2MSPS DAC
TIMING DIAGRAM
DATA 00000000 11111111 00000000 90% 11111111
DAC1252X_JVC
00000000
VOUT DATA
50%
Td
10%
Tr
Tf
VOUT
50%
DATA
00000000
11111111
00000000 ± 0.5LSB
VOUT
50%
Ts
PD
50%
50%
Ton VOUT
± 0.5LSB 0.0V
Toff
± 0.5LSB
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition. 2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB. 3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The DAC1252X_JVC has a 8BIT R-2R block, two decoders, two OP amps, and control block. 2. The digital outputs of two decoders decide the voltage level of R2R block.
V Rstring =
VRT - VRB 8 n (2 * D n ) 8 2 n=0
3. Normal Conditions : VRT=2.45V , VRB=0.05V, PD=High You can change the voltages of VRT and VRB to 2.5V and 0.0V , but the performance of DAC1252X_JVC will be degraded.
SEC ASIC
5 / 10
ANALOG
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