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Part: K3P5C1000F-DC15
Category:
Memory
-> ROM
-> Mask ROM
-> Pagemode
-> 16M bit
Description: Description = K3P5C1000F 16M-Bit(2Mx8,1Mx16) CMOS Mask ROM ;; Organization = 2Mx8,1Mx16 ;; Voltage(V) = 5.0 ;; Speed(ns) = 100/30 ;; Package = 42DIP,44SOP,44TSOP2 ;; Current (mA/uA) = 150/50 ;; Production Status = Mass Production ;; Comments = 4word
Company: Samsung Semiconductor, Inc.
Datasheet: Download K3P5C1000F-DC15 datasheet File size : 283 kB
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Datasheet text preview:
K3P5C1000F-D(G)C
16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM
FEATURES
· Switchable organization 2,097,152 x 8(byte mode) 1,048,576 x 16(word mode) · Fast access time Random Access : 100ns(Max.)@CL=50pF, 120ns(Max.)@CL=100pF Page Access : 30ns(Max.)@CL=50pF 40ns(Max.)@CL=100pF 4 Words / 8 Bytes page access · Supply voltage : single +5V · Current consumption Operating : 150mA(Max.) Standby : 50µA(Max.) · Fully static operation · All inputs and outputs TTL compatible · Three state outputs · Package -. K3P5C1000F-DC : 42-DIP-600 -. K3P5C1000F-GC : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P5C1000F-D(G)C is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 2,097,152 x 8 bit(byte mode) or as 1,048,576 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 4 words (or 8 bytes) of data to read fast in the same page, CE and A3 ~ A19 should not be changed. This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P5C1000F-DC is packaged in a 42-DIP and the K3P5C1000F-GC in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
A 19 . . . . . . . . A2 A0~A1 A-1 CE OE BHE Pin Name A0 - A1 A2 - A19 Q0 - Q14 Q15 /A-1 BHE CE OE V CC VSS N.C Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power ( +5V) Ground No Connection CONTROL LOGIC X BUFFERS AND DECODER
PIN CONFIGURATION
MEMORY CELL MATRIX (1,048,576x16/ 2,097,152x8)
A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9
42 A19 41 A 8 40 A9 39 A10 38 A 11 37 A 12 36 A13 35 A14 34 A 15 33 A 16 32 BHE
N.C 1 A 18 A 17 A7 A6 A5 A4 A3 A2 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21
44 N.C 43 A19 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 B H E 32 VSS 31 Q15/A-1 30 Q 7 29 Q 1 4 28 Q6 27 Q13 26 Q 5 25 Q 12 24 Q4 23 VCC
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS
...
Q 0 /Q8 Q7/Q15
A 0 10 CE 11 VSS 12 O E 13 Q 0 14 Q 8 15 Q1 16 Q9 17 Q2 18 Q 10 19 Q 3 20 Q11 21
A1 10
DIP
A0 31 VSS CE 30 Q15/A-1 VSS 29 Q 7 OE 28 Q 1 4 Q0 27 Q6 Q8 26 Q13 Q1 25 Q5 Q9 24 Q 12 Q2 23 Q 4 Q10 22 VCC Q3
SOP
Q11 22
K3P5C1000F-DC K3P5C1000F-GC
K3P5C1000F-D(G)C
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TStg Rating
CMOS MASK ROM
Unit V °C °C
-0.3 to +7.0 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 4.5 0 Typ 5.0 0 Max 5.5 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH = -400µA IOL = 2.1mA Test Conditions Cycle=5MHz, all outputs open CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.2 -0.3 2.4 Max 150 1 50 10 10 VCC+0.3 0.8 0.4 Unit mA mA µA µA µA V V V V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L L Input Operating BHE X X H Q15/A -1 X X Output Mode Standby Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol C OUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P5C1000F-D(G)C
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)
0.6V to 2.4V 10ns 0.8V and 2.0V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change
NOTE : Page Address is determined as below. Word mode(BHE=VIH) ; A0, A1 Byte mode(BHE=VIL) ; A-1, A0, A1
Symbol t RC tACE tAA tPA t OE tDF tOH
K3P5C1000F-D(G)C10 (CL = 5 0 p F ) Min 100 100 100 30 30 20 0 Max
K3P5C1000F-D(G)C12 (CL=100pF) Min 120 120 120 40 40 20 0 Max
K3P5C1000F-D(G)C15 (CL=100pF) Unit Min 150 150 150 50 50 30 0 Max ns ns ns ns ns ns ns
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