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Part: K3P5C2000D-SC15
Category:
Memory
-> ROM
-> Mask ROM
-> Pagemode
-> 16M bit
Description: Description = K3P5C2000D 16M-Bit(1Mx16,512Kx32) CMOS Mask ROM ;; Organization = 1Mx16,512Kx32 ;; Voltage(V) = 5.0 ;; Speed(ns) = 100/30ns(Max.)@CL=100pF ;; Package = 70SSOP ;; Current (mA/uA) = 150/50 ;; Production Status = Mass Production ;; Comments = EOL(Mar.'03)
Company: Samsung Semiconductor, Inc.
Datasheet: Download K3P5C2000D-SC15 datasheet File size : 283 kB
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Datasheet text preview:
K3P5C2000D-SC
16M-Bit (1Mx16 /512Kx32) CMOS MASK ROM
FEATURES
· Switchable organization 1,048,576 x 16(word mode) 524,288 x 32(double word mode) · Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.) 4 double Words / 8 Words page access · Supply voltage : single +5V · Current consumption Operating : 150mA(Max.) Standby : 50µA(Max.) · Fully static operation · All inputs and outputs TTL compatible · Three state outputs · Package -. K3P5C2000D-SC : 70-SSOP-500
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P5C2000D-SC is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 16 bit(word mode) or is 524,288 x 32 bit(double word mode) depending on WORD voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 4 double words (or 8 words) of data to read fast in the same page, CE and A2 ~ A18 should not be changed. This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P5C2000D-SC is packaged in a 70-SSOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A18 . . . . . . . . A2 A0,A1 A-1 CE OE WORD Pin Name A0 - A1 A2 - A18 Q0 - Q30 Q31 /A-1 WORD CE OE VCC V SS N.C
X BUFFERS AND DECODER
MEMORY CELL MATRIX (524,288x32/ 1,048,576x16)
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS ... Q 0 /Q1 6 Q 1 5 /Q3 1
CONTROL LOGIC
Pin Function Page Address Inputs Address Inputs Data Outputs Output 31(Double word mode)/ LSB Address(Word mode) Double word/Word mode selection Chip Enable Output Enable Power (+5V) Ground No Connection
A0 A1 A2 A3 A4 A5 VC C Q0 Q16 Q1 Q17 VSS VC C Q2 Q18 Q3 Q19 Q4 Q20 Q5 Q21 VSS VC C Q6 Q22 Q7 Q23 VSS A6 A7 A8 A9 A1 0 A1 1 A1 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SSOP
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
N.C N.C N.C WORD OE CE VSS Q 31/ A - 1 Q 15 Q 30 Q 14 VSS VC C Q 29 Q 13 Q 28 Q 12 Q 27 Q 11 Q 26 Q 10 VSS VC C Q 25 Q9 Q 24 Q8 VC C N.C A 18 A 17 A 16 A 15 A 14 A 13
K3P5C2000D-SC
K3P5C2000D-SC
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating
CMOS MASK ROM
Unit V °C °C
-0.3 to +7.0 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 4.5 0 Typ 5.0 0 Max 5.5 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 I LI ILO VIH VIL VOH VOL IOH=-400µA IOL=2.1mA Test Conditions Cycle=5MHz, all outputs open CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.2 -0.3 2.4 Max 150 1 50 10 10 VCC+0.3 0.8 0.4 Unit mA mA µA µA µA V V V V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L L Input Operating WORD X X H Q31/A-1 X X Output Mode Standby Operating Operating Data High-Z High-Z Q 0 ~Q3 1 :Dout Q0~Q15 : Dout Q16~Q 30 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol C OUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P5C2000D-SC
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to 70°C, VCC=5V±10%, unless otherwise noted.)
0.6V to 2.4V 10ns 0.8V and 2.0V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA
tPA
K3P5C2000D-SC10 Min 100 100 100 30 30 20 0 Max
K3P5C2000D-SC12 Min 120 120 120 50 50 20 0 Max
K3P5C2000D-SC15 Min 150 150 150 70 70 30 0 Max
Unit ns ns ns ns ns ns ns
tOE tDF tOH
NOTE : Page Address is determined as below. Double Word mode (WORD=VIH) : A0, A1 Word mode (WORD=VIL) : A-1, A0, A1
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