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Part: K3P6C1000B-TC
Category:
Memory
-> ROM
-> Mask ROM
-> Pagemode
-> 32M bit
Description: Description = K3P6C1000B 32M-Bit(4Mx8,2Mx16) CMOS Mask ROM ;; Organization = 4Mx8,2Mx16 ;; Voltage(V) = 5.0 ;; Speed(ns) = 100/30ns(Max.)@CL=100pF ;; Package = 44SOP,44TSOP2 ;; Current (mA/uA) = 150/50 ;; Production Status = Mass Production ;; Comments = EOL(Mar.'03)
Company: Samsung Semiconductor, Inc.
Datasheet: Download K3P6C1000B-TC datasheet File size : 283 kB
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Datasheet text preview:
K3P6C1000B-TC
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
FEATURES
· Switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) · Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.) · 8 words/ 16 bytes page access · Supply voltage : single +5V · Current consumption Operating : 150mA(Max.) Standby : 50µA(Max.) · Fully static operation · All inputs and outputs TTL compatible · Three state outputs · Package -. K3P6C1000B-TC : 44-TSOP2-400
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P6C1000B-TC is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 4,194,304x8 bit(byte mode) or as 2,097,152x16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 8 words(or 16 bytes) of data to read fast in the same page, CE and A3 ~ A20 should not be changed. This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P6C1000B-TC is packaged in a 44-TSOP2.
FUNCTIONAL BLOCK DIAGRAM
A20 . . . . . . . . A3 A0~A2 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (2,097,152x16/ 4,194,304x8)
PIN CONFIGURATION
N.C A1 8 A 17 A7 A6 A5 A4 A3 A2
1 2 3 4 5 6 7 8 9
44 A20 43 A19 42 A 8 41 A 9 40 A 10 39 A 11 38 A12 37 A13 36 A 14 35 A 15
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS ...
A 1 10 A0 11 CE 12 VSS 13 OE 14 Q0 Q8 Q1 Q9 15 16 17 18 19 20
TSOP2
34 A16 33 BHE 32 V S S 31 Q15 /A-1 30 Q7 29 Q14 28 Q6 27 Q 13 26 Q 5 25 Q 12 24 Q4 23 VCC
CE OE BHE Pin Name A0 - A2 A3 - A20 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C CONTROL LOGIC
Q 0 /Q8
Q7/Q 15
Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power ( +5V) Ground No Connection
Q2 Q10
Q3 21 Q11 22
K3P6C1000B-TC
K3P6C1000B-TC
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN T BIAS TSTG Rating
CMOS MASK ROM
Unit V °C °C
-0.3 to +7.0 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Supply Voltage Supply Voltage Symbol VCC V SS Min 4.5 0 Typ 5.0 0 Max 5.5 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC I SB1 I SB2 ILI ILO VIH VIL VOH VOL IOH=-400µ A IOL=2.1mA Test Conditions Min 2.2 -0.3 2.4 Max 150 1 50 10 10 VCC+0.3 0.8 0.4 Unit mA mA µA µA µA V V V V
Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q 7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
K3P6C1000B-TC
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)
0.6V to 2.4V 10ns 0.8V and 2.0V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change
NOTE : Page Address is determined as below. Word mode(BHE=VIH) ; A0, A1, A2 Byte mode(BHE=VIL) ; A -1, A0, A1, A2
Symbol tRC tACE tAA tPA tOE tDF tOH
K3P6C1000B-TC10 Min 100 100 100 30 30 20 0 Max
K3P6C1000B-TC12 Min 120 120 120 50 50 20 0 Max
K3P6C1000B-TC15 Min 150 150 150 70 70 30 0 Max
Unit ns ns ns ns ns ns ns
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