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Part: K4G813222B-PC70
Category:
Memory
-> DRAM
-> SGRAM
-> 8 Mb->Graphics Memory
Description: Description = K4G813222B 128K X 32Bit X 2 Banks Synchronous Graphic RAM ;; Organization = 256Kx32 ;; Voltage(V) = 3.3 ;; Speed(ns) = 70,80,10 ;; Package = 100PQFP ;; Production Status = Eol ;; Comments = LVTTL
Company: Samsung Semiconductor, Inc.
Datasheet: Download K4G813222B-PC70 datasheet File size : 283 kB
Request For quote: Find where to buy K4G813222B-PC70
Datasheet text preview:
K4G813222B
128K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
· · · · JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual bank / Pulse RAS MRS cycle with address key programs -. CAS Latency (2, 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM 0-3 for byte masking Auto & self refresh 16ms refresh period (1K cycle) 100 Pin PQFP, TQFP (14 x 20 mm) Reverse Type Package offers the best signal routing
CMOS SGRAM
GENERAL DESCRIPTION
The K4G813222B is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphics systems.
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ORDERING INFORMATION
Part NO. K4G813222B-PC70 K4G813222B-PC80 K4G813222B-PC10 K4G813222B-QC70 K4G813222B-QC80 K4G813222B-QC10
* -UC# : Reverse Type PQFP
Max Freq. 143MHz 125MHz 100MHz 143MHz 125MHz 100MHz
Interface LVTTL
Package 100 PQFP
Graphics Features
· SMRS cycle. -. Load mask register -. Load color register · Write Per Bit(Old Mask) · Block Write(8 Columns)
LVTTL
100 TQFP
FUNCTIONAL BLOCK DIAGRAM
DQMi BLOCK WRITE CONTROL LOGIC CLK CKE CS MASK WRITE MASK REGISTER COLOR REGISTER INPUT BUFFER
CONTROL
LOGIC
MUX
·
COLUMN MASK DQMi DQi (i=0~31)
TIMING REGISTER
SENSE AMPLIFIER
RAS CAS WE DSF DQMi
·
128Kx32 CELL ARRAY
128Kx32 CELL ARRAY
ROW DECORDER BANK SELECTION
·
SERIAL COUNTER COLUMN ADDRESS BUFFER ROW ADDRESS BUFFER REFRESH COUNTER
ADDRESS REGISTER CLOCK ADDRESS(A0~A9)
OUTPUT BUFFER
LATENCY & BURST LENGTH
PROGRAMING REGISTER
COLUMN DECORDER
K4G813222B
Forward Type
Reverse Type
PIN CONFIGURATION (TOP VIEW)
DQ2 VSSQ DQ1 DQ0 VDD N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VSS DQ31 DQ30 VSSQ DQ29 DQ29 VSSQ DQ30 DQ31 VSS N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C V DD DQ0 DQ1 VSSQ DQ2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 Pin QFP Reverse Type 20 x 14 mm2 0.65mm pin Pitch 100 Pin QFP Forward Type 20 x 14 mm2 0.65mm pin Pitch
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C DQM3 DQM1 CLK CKE DSF N.C A8 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ3 V DDQ DQ4 DQ5 VSSQ DQ6 DQ7 V DDQ DQ16 DQ17 VSSQ DQ18 DQ19 V DDQ V DD VSS DQ20 DQ21 VSSQ DQ22 DQ23 V DDQ DQM0 DQM2 WE CAS RAS CS BA(A9) N.C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS BA(A9) N.C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C DQM3 DQM1 CLK CKE DSF N.C A8
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A7 A6 A5 A4 VSS N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VDD A3 A2 A1 A0
CMOS SGRAM
A0 A1 A2 A3 VDD N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VSS A4 A5 A6 A7
K4G813222B
PIN CONFIGURATION DESCRIPTION
PIN CLK CS NAME System Clock Chip Select INPUT FUNCTION Active on the positive going edge to sample all inputs.
CMOS SGRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMi Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one clock +tSS prior to new command. Disable input buffers for power down in standby. Row / Column addresses are multiplexed on the same pins. Row address : RA0 ~ RA8, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and Row precharge. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active.(Byte Masking) Data inputs/outputs are multiplexed on the same pins. Enables write per bit, block write and special mode register set. Power Supply : +3.3Vą0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity.
CKE
Clock Enable
A0 ~ A8 A9(BA) RAS CAS WE DQMi DQi DSF VDD/VSS VDDQ/VSSQ N.C
Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Define Special Function Power Supply /Ground Data Output Power /Ground No Connection
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