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Part: K4S283234F-M

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Company: Samsung Semiconductor, Inc.

Datasheet: Download K4S283234F-M datasheet     File size : 369 kB

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Datasheet text preview:
K4S283234F-M
C M O S SDRAM
4Mx32 SDRAM 90FBGA
(VDD 2.5V, VDDQ 2.5V)
Revision 0.0 November 2001
Rev. 0.0 Nov. 2001
K4S283234F-M
Revision History
R e v i s i o n 0.0 (Nov. 16. 2001, Final)
· Final generation for 4Mx32 2.5V SDRAM FBGA.
C M O S SDRAM
Rev. 0.0 Nov. 2001
K4S283234F-M
1M x 32Bit x 4 Banks SDRAM in 90FBGA
FEATURES
·. · · · 2.5V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (1 & 2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock ·. Burst read single-bit write operation · DQM for masking ·. Auto & self refresh ·. 64ms refresh period (4K cycle). ·. Extended Temperature Operation (-25 °C ~ 85°C). ·. 90Balls FBGA based on 2 pcs of 4Mx16 SDRAM.
C M O S SDRAM
GENERAL DESCRIPTION
The K4S283234F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq.
*1
Interface Package LVTTL 90 Balls FBGA
K4S283234F-ME/N1L 1 0 0 M H z ( C L = 3 )
K4S283234F-ME/N15 66MHz(CL=2) * 2
- ME ; Normal Power, Extended Temperature. - MN ; Low Power, Extended Temperature. Note : 1. In case of 40MHz Frequency, CL1 can be supported. 2. In case of 33MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control LWE LDQM
Data Input Register B a n k Select 1M x 32 1M x 32 1M x 32 1M x 32
R efr es h Counter
O ut put Buffer
Ro w Decoder
S ens e AMP
Ro w Buffer
DQi
Ad dr es s Register
CLK ADD
Column Decoder Col . Buffer Latency & Burst Length
LRA S
LCB R
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Nov. 2001


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