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Part: K4S510432M-TC/TL1H
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 512 Mb
Description: Description = K4S510432M 32M X 4Bit X 4 Banks Synchronous DRAM ;; Organization = 128Mx4 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 75,1H,1L ;; Package = 54TSOP2 ;; Power = C,l ;; Production Status = Mass Production ;; Comments = Monolithic
Company: Samsung Semiconductor, Inc.
Datasheet: Download K4S510432M-TC/TL1H datasheet File size : 394 kB
Request For quote: Find where to buy K4S510432M-TC/TL1H
Datasheet text preview:
K4S510432M
CMOS SDRAM
512Mbit SDRAM
32M x 4bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.3 May. 2002
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.3 May. 2002
K4S510432M
Revision History
Revision 0.0 (Mar. 2001) Revision 0.1 (Aug. 2001)
Defined target DC characteristics.
CMOS SDRAM
Revision 0.2 (Dec. 2001)
· · Changed "Target" to "Preliminary". Redefined DC characteristics.
Revision 0.3 (May. 2002)
· · Changed "Preliminary" to "Final". Redefined DC characteristics.
Rev. 0.3 May. 2002
K4S510432M
32M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
· JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Four banks operation · MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock. · Burst read single-bit write operation · DQM for masking · Auto & self refresh · 64ms refresh period (8K cycle) Part No. K4S510432M-TC/TL75 K4S510432M-TC/TL1H K4S510432M-TC/TL1L
CMOS SDRAM
GENERAL DESCRIPTION
The K4S510432M is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 4 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Max Freq. 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL Interface Package 54pin TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select 32M x 4 Sense AMP 32M x 4 32M x 4 32M x 4 R efresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
L RA S
L CB R
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM * Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.3 May. 2002
Others parts begin by k4
K4-1 K4-2 K4-3 K4-4 K4-5 K4-6 K4-7 K4-8 K4-9
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