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Part: K4S510732C-TC/L75
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 512 Mb
Description: Description = K4S510732C 16M X 8Bi TX 4 Banks Synchronous DRAM ;; Organization = 64Mx8 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 7C,75,1H,1L ;; Package = 54TSOP2 ;; Power = C,l ;; Production Status = Mass Production ;; Comments = Stacked
Company: Samsung Semiconductor, Inc.
Datasheet: Download K4S510732C-TC/L75 datasheet File size : 394 kB
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Datasheet text preview:
K4S510732C
CMOS SDRAM
Stacked 512Mbit SDRAM
16M x 8bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.1 Sept. 2001
* Samsung Electronics reserves the right to change products or specification without
Rev. 0.1 Sept.2001
K4S510732C
CMOS SDRAM
Revision 0.0 (Mar., 2001) Revision 0.1 (Sep., 2001)
· · · Corrected Typo. Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept.2001
K4S510732C
16M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
· JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Four banks operation · MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock. · Burst read single-bit write operation · DQM for masking · Auto & self refresh · 64ms refresh period (8K Cycle) Part No. K4S510732C-TC/L7C K4S510732C-TC/L75 K4S510732C-TC/L1H K4S510732C-TC/L1L
CMOS SDRAM
GENERAL DESCRIPTION
The K4S510732C is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Max Freq. 133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin TSOP(II) Interface Package
FUNCTIONAL BLOCK DIAGRAM
CLK,CAS,RAS /WE,DQM /CS1,CKE1
32Mx8
32Mx8
/CS0,CKE0
DQ0 ~ DQ7
A0~A12,BA0,BA1
* Samsung Electronics reserves the right to change products or specification without notice.
Staktek' stacking technology is Samsung' stacking technology of choice. s s
Rev. 0.1 Sept.2001
Others parts begin by k4
K4-1 K4-2 K4-3 K4-4 K4-5 K4-6 K4-7 K4-8 K4-9
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