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Part: K4S510832C
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 512 Mb
Description: Description = K4S510832C 16M X 8Bit X 4 Banks Synchronous DRAM ;; Organization = 64Mx8 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 8K/64ms ;; Speed = 7C,75,1H,1L ;; Package = 54TSOP2 ;; Power = C,l ;; Production Status = Mass Production ;; Comments = DDP
Company: Samsung Semiconductor, Inc.
Datasheet: Download K4S510832C datasheet File size : 394 kB
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Datasheet text preview:
K4S510832C
CMOS SDRAM
DDP 512Mbit SDRAM
16M x 8bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.2 Nov. 2001
This is to advise Samsung customers that, until August 1, 2003, in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones, telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are, however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.2 Nov. 2001
K4S510832C
CMOS SDRAM
Revision 0.0 (Mar., 2001) Revision 0.1 (Sep., 2001)
· R e d e f i n e d IDD1 & IDD4 in DC Characteristics
Revision 0.2 (Nov. 2001)
· C h a n g e d the Notes in Operating AC Parameter. 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.2 Nov. 2001
K4S510832C
1 6 M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
· JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Four banks operation · MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock. · Burst read single-bit write operation · DQM for masking · Auto & self refresh · 64ms refresh period (8K Cycle)
CMOS SDRAM
GENERAL DESCRIPTION
T h e K4S510832C is 536,870,912 bits synchronous high data rate D y n a m i c RAM organized as 4 x 16,785,216 words by 8 bits, fabric a t e d with SAMSUNG's high performance CMOS technology. Sync h r o n o u s design allows precise cycle control with the use of s y s t e m clock I/O transactions are possible on every clock cycle. R a n g e of operating frequencies, programmable burst length and p r o g r a m m a b l e latencies allow the same device to be useful for a v a r i e t y of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
P a r t No. K4S510832C-KC/L7C K4S510832C-KC/L75 K4S510832C-KC/L1H K4S510832C-KC/L1L M a x Freq. 133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin TSOP(II) Interface P a c k a g e
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE LDQM
D a t a Input Register
B a n k Select 2 x 8M x 8 S e n s e AMP 2 x 8M x 8 2 x 8M x 8 2 x 8M x 8
R e fr e sh Counter
Ou tp u t Buffer
R o w Decoder
R o w Buffer
DQi
A d dr e ss Register
CLK ADD
C o l u m n Decoder C o l. Buffer L a t e n c y & Burst Length
L R AS
L C BR
LCKE LRAS LCBR LWE LCAS
P r o g r a m m i n g Register LWCBR LDQM
T i m i n g Register
CLK
CKEn
CS n
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.2 Nov. 2001
Others parts begin by k4
K4-1 K4-2 K4-3 K4-4 K4-5 K4-6 K4-7 K4-8 K4-9
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