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Part: K7B321825M-HC85
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 32 Mb
-> SB & SPB
Description: Description = K7B321825M 2Mx18-Bit Synchronous Burst SRAM ;; Organization = 2Mx18 ;; Operating Mode = SB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 6.5,7.5,8.5 ;; Speed-tcyc (MHz) = 133,118,100 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP,119BGA,165FBGA ;; Production Status = Mass Production ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7B321825M-HC85 datasheet File size : 401 kB
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Datasheet text preview:
K7B323625M K7B321825M
Document Title
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. 0.0 0.1 0.2 0.3 History 1. Initial draft 1 . Add 165FBGA package 1 . Update JTAG scan order 1 . Change pin out for 165FBGA - x18/x36 ; 11B => from A to NC , 2R ==> from NC to A . 1 . Insert pin at JTAG scan order of 165FBGA in connection with pin out change - x18/x36 ; insert Pin ID of 2R to BIT number of 69 1 . Add Icc, Isb, Isb1 and Isb2 values. 1 . Correct the pin name of 100TQFP. 1 . Change the Stand-by current (Isb) Before After I s b - 65 : 100 140 - 75 : 90 130 - 85 : 80 130 Isb1 : 90 110 Isb2 : 80 100 Draft Date May. 10. 2001 Aug. 29. 2001 Dec . 03. 2001 F e b . 14 . 2002 Remark Advance Preliminary Preliminary Preliminary
0.4
A p r . 20. 2002
Preliminary
0.5 1.0 1.1
M a y . 10. 2002 O c t . 15. 2002 O c t . 17, 2003
Preliminary Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Oct. 2003 Rev 1.1
K7B323625M K7B321825M
1Mx36 & 2Mx18 Synchronous SRAM
32Mb SB/SPB Synchronous SRAM Ordering Information
Org. P a r t Number K7B321825M-Q(H/F)C65/75/85 K7A321801M-QC25/22/20/16/15/14 K7B323625M-Q(H/F)C65/75/85 K7A323601M-QC25/22/20/16/15/14 Mode SB SPB(2E2D) SB SPB(2E2D) VDD 3.3 3.3 3.3 3.3 3.3 3.3 Speed S B ; Access Time(ns) S P B ; Cycle Time(MHz) 6.5/7.5/8.5ns 250/225/200/167/150/138MHz 250/225/200/167/150/138MHz 6.5/7.5/8.5ns 250/225/200/167/150/138MHz 250/225/200/167/150/138MHz C Q : 100TQFP (Commercial H : 119BGA Temperature F : 165FBGA Range) PKG Temp
2 M x 1 8 K 7 A 3 2 1 8 0 0 M - Q ( H / F ) C 2 5 / 2 2 / 2 0 / 1 6 / 1 5 / 1 4 SPB(2E1D)
1 M x 3 6 K 7 A 3 2 3 6 0 0 M - Q ( H / F ) C 2 5 / 2 2 / 2 0 / 1 6 / 1 5 / 1 4 SPB(2E1D)
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Oct. 2003 Rev 1.1
K7B323625M K7B321825M
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Burst SRAM
FEATURES
· Synchronous Operation. · On-Chip Address Counter. · Self-Timed Write Cycle. · On-Chip Address and Control Registers. · 3.3V+0.165V/-0.165V Power Supply. · I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O · 5V Tolerant Inputs Except I/O Pins. · Byte Writable Function. · Global Write Enable Controls a full bus-width write. · Power Down State via ZZ Signal. · LBO Pin allows a choice of either a interleaved burst or a linear burst. · Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. · Asynchronous Output Enable Control. · ADSP , ADSC, ADV Burst Control Pins. · TTL-Level Three-State Output. · 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package) · 165FBGA(11x15 ball aray) with body size of 15mmx17mm.
G E N E R A L DESCRIPTION
The K7B323625M and K7B321825M are 37,748,736-bit Synchronous Static Random Access Memory designed for high p e r f o r m a n c e second level cache of Pentium and Power PC b a s e d System. It is organized as 1M(2M) words of 36(18) bits and integrates a d d r e s s and control registers, a 2-bit burst address counter and a d d e d some new functions for high performance cache RAM a p p l i c a t i o n s ; G W, B W, LBO, ZZ. Write cycles are internally selft i m e d and synchronous. Full bus-width write is done by GW, and each byte write is perf o r m e d by the combination of W Ex and BW when G W is high. A n d with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status proc e s s o r (A D S P ) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in t h e systems burst sequence and are controlled by the burst a d d r e s s advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). Z Z pin controls Power Down State and reduces Stand-by curr e n t regardless of CLK. T h e K7B323625M and K7B321825M are fabricated using SAMS U N G s high performance CMOS technology and is available i n a 100pin TQFP, 119BGA and 165FBGA package. Multiple p o w e r and ground pins are utilized to minimize ground bounce.
F A S T ACCESS TIMES
PARAMETER C y c l e Time Clock Access Time O u t p u t Enable Access Time Symbol tCYC tCD tOE -65 7.5 6.5 3.5 -75 8.5 7.5 3.5 -85 U n i t 10 8.5 4.0 ns ns ns
L O G I C BLOCK DIAGRAM
CLK LBO CO NTROL REG IS TE R ADV ADSC 1Mx36 , 2Mx18 MEMORY ARRAY
BURST CONTROL LOGIC
BURST ADDRESS COUNTER A0~A1
A0~A1
ADSP
A0~A19 or A0~A20
ADDRESS REGISTER
A2~A 9 1 or A2~A20
CS1 CS2 CS2 GW BW Wx E (x=a,b,c,d or a,b) OE ZZ
DATA-IN REGISTER CO NTROL RE GIS TER
CONTROL LOGIC
OUTPUT BUFFER
DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa ~ DQPd DQPa,DQPb
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Oct. 2003 Rev 1.1
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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