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Part: K7B401825A
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 4 Mb
-> SB & SPB
Description: Description = K7B401825A 128K X 36-Bit Synchronous Burst SRAM ;; Organization = 256Kx18 ;; Operating Mode = FT(SB) ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 6.5,7.5,8.0,9.0 ;; Speed-tcyc (MHz) = 133,117,100,83 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7B401825A datasheet File size : 270 kB
Request For quote: Find where to buy K7B401825A
Datasheet text preview:
K7B403625A K7B401825A
Document Title
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. 0.0 0.1 History Initial draft 1. Changed DC condition at Icc and ISB. Icc ; from 320mA to 370mA at -65, from 300mA to 350mA at -75, from 280mA to 330mA at -80, from 260mA to 310mA at -90, ISB ; from 130mA from 120mA from 110mA from 100mA 1.0 Final spec release to to to to 140mA 130mA 120mA 110mA at at at at -65, -75, -80, -90, May. 15. 2000 Final Draft Date jan. 22. 2000 April. 03. 2000 Remark Preliminary Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
May 2000 Rev 1.0
K7B403625A K7B401825A
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Burst SRAM
FEATURES
· Synchronous Operation. · On-Chip Address Counter. · Write Self-Timed Cycle. · On-Chip Address and Control Registers. · VDD= 3.3V+0.3V/-0.165V Power Supply. · VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · 5V Tolerant Inputs except I/O Pins. · Byte Writable Function. · Global Write Enable Controls a full bus-width write. · Power Down State via ZZ Signal. · Asynchronous Output Enable Control. · ADSP, ADSC, ADV Burst Control Pins. · LBO Pin allows a choice of either a interleaved burst or a linear burst. · Three Chip Enables for simple depth expansion with No Data Contention. · TTL-Level Three-State Output. · 100-TQFP-1420A
GENERAL DESCRIPTION
The K7B403625A and K7B401825A are 4,718,592 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 128K(256K) words of 36(18) bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B403625A and K7B401825A are implemented with SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time S y m b o l -65 -75 -80 -90 U n i t tCYC tCD tOE 7.5 8.5 1 0 12 ns ns ns
6.5 7.5 8.0 9 . 0 3.5 3.5 3.5 3 . 5
LOGIC BLOCK DIAGRAM
CLK LBO
CONTROL REGISTER
ADV ADSC
BURST CONTROL LOGIC
BURST ADDRESS A0~A1 COUNTER
A 0~A1
128Kx36 , 256Kx18 MEMORY ARRAY
ADSP
A0~A16 or A0~A17
ADDRESS REGISTER
A2~A16 or A2~A17
CS 1 CS 2 CS 2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd
DATA-IN REGISTER C ON T R OL REGISTER
or DQa0 ~ DQb7 DQPa ~ DQPb
CONTROL LOGIC
OUTPUT BUFFER
36 or 18
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May 2000 Rev 1.0
K7B403625A K7B401825A
PIN CONFIGURATION(TOP VIEW)
128Kx36 & 256Kx18 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV 83
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VSS
LBO
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
N.C.
N.C.
N.C.
PIN NAME
SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa 0~a7 DQb 0~b7 DQc0~c7 DQd 0~d7 DQPa~P d VDDQ Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control 86 88 87 64 31 VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,43,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 Burst Address Advance 83 Address Status Processor 84 Address Status Controller 85 Clock 89 Chip Select 98 Chip Select 97 Chip Select 92 Byte Write Inputs 93,94,95,96
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx (x=a,b,c,d) OE GW BW ZZ LBO
N.C.
Output Power Supply (2.5V or 3.3V) Output Ground
A16
50
DQPc DQc0 DQc1 VDDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ V SSQ DQd2 DQd3 DQd4 DQd5 V SSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B403625A(128Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
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May 2000 Rev 1.0
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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