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Part: K7B401825M
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 4 Mb
-> SB & SPB
Description: Description = K7B401825M 256K X 18-Bit Synchronous Burst SRAM ;; Organization = 256Kx18 ;; Operating Mode = SB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 7.5,8.0,9.0 ;; Speed-tcyc (MHz) = 117,100,83 ;; I/o Voltage(V) = 2.5,3.3 ;; Package = 100TQFP ;; Production Status = Eol ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7B401825M datasheet File size : 392 kB
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Datasheet text preview:
K7B401825M
Document Title
256Kx18-Bit Synchronous Burst SRAM
256Kx18 Synchronous SRAM
Revision History
Rev. No. 0.0 0.1 History Initial draft Modify power down cycle timing & Interleaved read timing, Insert Note 4 at AC timing characteristics. Change ISB1 value from 10mA to 30mA. Change ISB2 value from 10mA to 20mA. Change Undershoot spec from -3.0V(pulse width20ns) to -2.0V(pulse widthtCYC/2) Add Overshoot spec 4.6V((pulse widthtCYC/2) Change VIH max from 5.5V to VDD+0.5V Draft Date May. 15. 1997 February. 11. 1998 Remark Preliminary Preliminary
0.2
April. 14. 1998
Preliminary
0.3
May 13. 1998 Change ISB2 value from 20mA to 30mA. Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V. Final spec Release Add VDDQ Supply voltage( 2.5V ) May 15. 1998 Dec. 02. 1998
Preliminary
1.0 2.0
Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
December 1998 Rev. 2.0
K7B401825M
256Kx18-Bit Synchronous Burst SRAM
FEATURES
· Synchronous Operation. · On-Chip Address Counter. · Write Self-Timed Cycle. · On-Chip Address and Control Registers. · VDD= 3.3V+0.3V/-0.165V Power Supply. · VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · 5V Tolerant Inputs except I/O Pins. · Byte Writable Function. · Global Write Enable Controls a full bus-width write. · Power Down State via ZZ Signal. · Asynchronous Output Enable Control. · ADSP, ADSC, ADV Burst Control Pins. · LBO Pin allows a choice of either a interleaved burst or a linear burst. · Three Chip Enables for simple depth expansion with No Data Contention. · TTL-Level Three-State Output. · 100-TQFP-1420A
256Kx18 Synchronous SRAM
GENERAL DESCRIPTION
The K7B401825M is a 4,718,592 bit Synchronous Static Random Access Memory designed for support zero wait state performance for advanced Pentium/Power PC address pipelining. And with CS1 high, ADSP is blocked to control signal. It is organized as 256K words of 18 bits and integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components count implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B401825M is implemented in SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time S y m b o l -75 tCYC tCD tOE 8.5 7.5 3.5 -80 10 8 3.5 -90 12 9 3.5 Unit ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO CONTROL REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1
256Kx18 MEMORY ARRAY
A0 ~ A1 ADDRESS REGISTER A2~A17
ADSP
A0~A17
CS1 CS2 CS2 GW BW WEa WEb OE ZZ DQa0 ~ DQb7 DQPa, DQPb
DATA-IN REGISTER CONTROL REGISTER
CONTROL LOGIC
OUTPUT BUFFER
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December 1998 Rev. 2.0
K7B401825M
PIN CONFIGURATION(TOP VIEW)
256Kx18 Synchronous SRAM
AD SC
AD SP
WEb
WEa
AD V 83
N. C.
N. C.
CL K
CS 1
CS 2
CS 2
VDD
GW
VSS
BW
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N .C.
N .C.
N .C.
N .C.
VDD
A5
A4
A3
A2
A1
A0
A11
A12
A13
A14
A15
A16
PIN NAME
SYMBOL A0 - A17 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 50,80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 SYMBOL VDD VSS N.C. PIN NAME Power Supply(+3.3V) Ground No Connect TQFP PIN NO. 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28, 29,30,38,39,42,43,51 52,53,56,57,66,75 78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
LBO
VSS
DQa0 ~ a 7 DQb0 ~ b 7 DQPa, Pb VDDQ VSSQ
Data Inputs/Outputs
Output Power Supply (2.5V or 3.3V) Output Ground
A17
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa 7 DQa 6 VSSQ VDDQ DQa 5 DQa 4 VSS N.C. VDD ZZ DQa 3 DQa 2 VDDQ VSSQ DQa 1 DQa 0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
-3-
December 1998 Rev. 2.0
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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