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Part: K7B403225B
Category:
Memory
-> SRAM
-> Sync. SRAM
-> 4 Mb
-> SB & SPB
Description: Description = K7B403225B 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM ;; Organization = 128Kx32 ;; Operating Mode = SB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 6.5,7.5,8.0 ;; Speed-tcyc (MHz) = 133,118,100 ;; I/o Voltage(V) = 3.3,2.5 ;; Package = 100TQFP ;; Production Status = Customer Sample ;; Comments = -
Company: Samsung Semiconductor, Inc.
Datasheet: Download K7B403225B datasheet File size : 392 kB
Request For quote: Find where to buy K7B403225B
Datasheet text preview:
K7B403625B K7B403225B K7B401825B
Document Title
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. 0.0 0.1 History 1. Initial draft 1. Changed DC parameters Icc ; from 300mA to 250mA at -65, from 280mA to 230mA at -75, from 260mA to 210mA at -80, from 240mA to 190mA at -90, Icc ; from 140mA from 130mA from 120mA from 110mA to to to to 130mA at -65, 120mA at -75, 110mA at -80, 100mA at -90, Draft Date May. 15. 2001 June. 12. 2001 Remark Preliminary Preliminary
0.2 1.0
ISB1 ; from 100mA to 80mA 1. Add x32 org. and industrial temperature 1. Final spec release 2. Changed Pin Capacitance - Cin ; from 5pF to 4pF - Cout ; from 7pF to 6pF
Aug. 11. 2001 Nov. 15. 2001
Preliminary Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov 2001 Rev 1.0
K7B403625B K7B403225B K7B401825B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb SB/SPB Synchronous SRAM Ordering Information
Org. Part Number Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) 6.5/7.5/8.0 ns 167/138 MHz 300/275/250/225/200 MHz 6.5/7.5/8.0 ns 167/138 MHz 300/275/250/225/200 MHz 167/138/ MHz 6.5/7.5/8.0 ns 167/138 MHz 300/275/250/225/200 MHz 167/138 MHz Q (100TQFP) C (Commercial Temperature Range) I: (Industrial Temperature Range) PKG Temp
K7B401825B-QC(I)65/75/80 256Kx18 K 7 A 4 0 1 8 0 0 B - Q C ( I ) 1 6 / 1 4 K7A401809B-QC(I)30/27/25/22/20 K7B403225B-QC(I)65/75/80 128Kx32 K7A403200B-QC(I)16/14 K7A403209B-QC(I)30/27/25/22/20 K7A403201B-QC(I)16/14 K7B403625B-QC(I)65/75/80 128Kx36 K7A403600B-QC(I)16/14 K7A403609B-QC(I)30/27/25/22/20 K7A403601B-QC(I)16/14
SB SPB(2E1D) SPB(2E1D) SB SPB(2E1D) SPB(2E1D) SPB(2E2D) SB SPB(2E1D) SPB(2E1D) SPB(2E2D)
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
-2-
Nov 2001 Rev 1.0
K7B403625B K7B403225B K7B401825B
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM
FEATURES
· Synchronous Operation. · On-Chip Address Counter. · Write Self-Timed Cycle. · On-Chip Address and Control Registers. · VDD= 3.3V+0.3V/-0.165V Power Supply. · VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. · 5V Tolerant Inputs except I/O Pins. · Byte Writable Function. · Global Write Enable Controls a full bus-width write. · Power Down State via ZZ Signal. · Asynchronous Output Enable Control. · ADSP, ADSC, ADV Burst Control Pins. · LBO Pin allows a choice of either a interleaved burst or a linear burst. · Three Chip Enables for simple depth expansion with No Data Contention. · TTL-Level Three-State Output. · 100-TQFP-1420A · Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7B403625B, K7B403225B and K7B401825B are 4,718,592 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 128K(256K) words of 36(18) bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B403625B, K7B403225B and K7B401825B are implemented with SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol -65 - 7 5 -80 U n i t t CYC tCD tOE 7 . 5 8 . 5 10 6.5 7.5 8.0 3.5 3.5 4.0 ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO
CONTROL REGISTER
ADV ADSC
BURST CONTROL LOGIC
BURST ADDRESS A0~A1 COUNTER
A 0~A1
128Kx36/32 , 256Kx18 MEMORY ARRAY
ADSP
A0~A16 or A0~A17
ADDRESS REGISTER
A2~A16 or A2~A17
CS 1 CS 2 CS 2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd
DATA-IN REGISTER C ON T R OL REGISTER
or DQa0 ~ DQb7 DQPa ~ DQPb
CONTROL LOGIC
OUTPUT BUFFER
36/32 or 18
-3-
Nov 2001 Rev 1.0
Others parts begin by k7
K7-1 K7-2 K7-3 K7-4 K7-5 K7-6 K7-7
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